[1] | Ramesh Vaddi, Vincent Pott, Julius Tsai Ming Lin, and Tony T. Kim, "Verilog-A modeling of an anchorless electro-mechanical non-volatile memory", Proc.17th Asia and South Pacific Design Automation Conference (ASP-DAC), Sydney, Australia, Jan,30-Feb,2, 2012 (Submitted). |
[2] | Ramesh Vaddi and Tony T. Kim"Ultra-low Power High Efficient Rectifiers with 3T/4T Double-gate MOSFETs for RFID Applications", Proc.IEEE International Symposium on Integrated Circuits (ISIC), Singapore, Dec 12-14, 2011 (Accepted). |
[3] | Ramesh Vaddi, S. Dasgupta, and R.P. Agarwal, " Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET", Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IIT Madras, India", pp.37-42, July 4-6, 2011. |
[4] | Ramesh Vaddi, S. Dasgupta and R.P. Agarwal," Two Dimensional Analytical Subthreshold Swing Model of a Generic (3T-4T) Double Gate MOSFET with Gate-S/D Underlap", Proc. IEEE Int. conference on Electronic Devices, Systems and Applications (ICEDSA), Kuala Lumpur, Malaysia, pp. 246-249, 25-27 April 2011. |
[5] | Ramesh Vaddi, S. Dasgupta and R.P. Agarwal," Two Dimensional Analytical Subthreshold current Model of a Generic (3T-4T) Double Gate MOSFET with Gate-S/D Underlap", Proc. IEEE Int. conference on Electronic Devices, Systems and Applications (ICEDSA), Kuala Lumpur, Malaysia, pp. 67-72, 25-27 April 2011. |
[6] | Ramesh Vaddi, S. Dasgupta and R.P. Agarwal," "Analytical Potential Distribution Model for Underlap Double Gate MOSFETs with 3T-4T and Symmetric-Asymmetric Options for Subthreshold operation: A Conformal Mapping Approach", Proceedings of Nanotech Conf & Expo (NSTI), Anaheim, California, USA, Vol.2, pp. 697-700, 21-24, June 2010. |
[7] | Ramesh Vaddi, M.P. Shrivastav and Saroj Rangnekar, "Modeling and Simulation of Digital Governors of an automated Small Hydro plant using MATLAB-SIMULINK-dSPACE", Proc. of International Conference on convergence of science and Engineering in Education and Research (ICSE-2010), Bangalore, India,2010. |
[8] | Ramesh Vaddi, S. Dasgupta and R.P. Agarwal," Robustness to PVT variations of Nano Scale Subthreshold CMOS Logic for Ultra Low Power Application ",Proc. of International Conference on convergence of science and Engineering in Education and Research (ICSE-2010), Bangalore, India,2010. |
[9] | Ramesh Vaddi, M.P. Shrivastav and Saroj Rangnekar, "SIMULINK Modeling and Simulation of an automated Small Hydro plant", Proc. of International Conference on emerging trends in Energy and environment (ICETEE-2010), Chennai, India, 2010. |
[10] | Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, "Robustness Comparisons of bulk CMOS and DGFinFET technologies with Circuit Co-Design for Energy Efficient Subthreshold Logic ", IEEE International workshop on the Physics of Semiconductor Devices (IWPSD), New Delhi, India, Dec. 2009. |
[11] | Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, "Investigation of Robustness and Performance Comparisons of DG-FinFETs with Symmetric, Asymmetric, Tied and Independent gate options for Optimal Subthreshold Logic", IEEE 4th International Conference on Computers & Devices for Communication (CODEC), Kolkata, India, 2009. |
[12] | Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, "SDG vs ADG with Tied and Independent gate Options in the Subthreshold Logic for Ultra Low Power Applications", 2nd IEEE Int. workshop. on Electronic Devices and Semiconductor Technology(IEDST), IIT Bombay, India, June 2009. |