Electrical and Electronic Engineering

Electrical and Electronic Engineering is an open access journal that provides rapid publication of articles in all areas of the subject. The journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence.

Ashwani K. Rana

Editorial Board Member of Electrical and Electronic Engineering

Associate Professor, National Institute of Technology, Hamirpur, India

Research Areas

VLSI Design, Device modeling, Nanoelevtronics

Education

2011Ph.D.N.I.T Hamirpur (H.P.), Leakage study in Nano scale MOSFET devices
2006M.Tech.I.I.T. Roorkee(U.K.), VLSI Technology and Solid State Devices
1998B.Tech.N.I.T Hamirpur, Electronics and Communication Engineering

Experience

2011-presentAssociate Professor on NIT Hamirpur
1999-2011Assistant Professor on NIT Hamirpur
1998-1999Trainee Engineer in Samsung

Publications: Journals

[1]  Ashwani K. Rana, Narottam Chand and Vinod Kapoor, "Gate Leakage Behavior of Source/Drain-to-gate Non-overlapped MOSFET Structure" Journal of Computational Electronics, Vol. 10, No. 1-2, pp. 222-228, 2011 (Springer).
[2]  Ashwani K. Rana, Narottam Chand and Vinod Kapoor, "Gate Current Modeling and Optimal Design of Nanoscale Non-Overlapped Gate to Source/Drain MOSFET, " Journal of Semiconductors, Vol. 32, No. 7, pp. 074001-6, 2011. Chinese academy of Science)
[3]  Ashwani K. Rana, Narottam Chand and Vinod Kapoor, "Modeling Gate Current for Nano Scale MOSFET with Different Gate Spacer, " Journal of Circuits, Systems, and Computers (JCSC), Vol. 20, No. 8, pp. 1659-1675 2011. World Scientic publishing company)
[4]  Ashwani K. Rana, Narottam Chand and Vinod Kapoor, "Modeling Gate Current of Nano Scale MOSFET for Circuit Simulation, " Multidiscipline Modeling in Materials and Structures, Vol. 7, No. 2, pp. 115-130, 2011(Emerald).
[5]  Ashwani K. Rana, Narottam Chand and Vinod Kapoor, "Impact of Gate Engineering on Gate Leakage Behavior of Nano Scale MOSFETs with High-k Dielectrics, " Journal of Nanoelectronics and Optoelectronics, Vol. 5, No. 3, pp. 343-348, 2010 ( ASP-American Scientific Publisher)
[6]  Ashwani K. Rana, Narottam Chand and Vinod Kapoor, "Gate Current Modeling Through High-K Gate Stack MOSFET for VLSI Logic Circuit Analysis, " Australian Journal of Electrical & Electronics Engineering (AJEEE). In Press. Institution of Engineers, Australia
[7]  Ashwani K. Rana, Narottam Chand and Vinod Kapoor, "An Optimal Design of High-K Based MOSFET for Reducing Gate Leakage in VLSI Logic Circuits, " The Mediterranean Journal of Electronics and Communications, Vol. 7, No. 1, pp. 182-189, 2011. Soft Motor Ltd.
[8]  Ashwani K. Rana, Narottam Chand and Vinod Kapoor, "Gate Leakage Aware Optimal Design of Modified Hybrid Nanoscale MOSFET and Its Application to Logic Circuits, " Iranian Journal of Electrical and Electronic Engineering, Vol. 7, No. 2, pp. 112-121, 2011. (Iranian university of Science and technology)
[9]  Ashwani K. Rana, Narottam Chand and Vinod Kapoor, "Gate Leakage Reduction through the use of Source/Drain-to-Gate Non-overlapped MOSFET Structure, " Journal of Nanoengineering and Nanosystems, Vol. 224, No. 4, pp. 173-181, 2010. Sage Journals
[10]  Ashwani K. Rana, Narottam Chand and Vinod Kapoor, "Analytical Gate Current Modeling in Nano Scale MOSFET with High-k Gate Stack Structure, " Journal of Electrical and Electronics Engineering, Vol. 3, No. 2, pp. 169-174, 2010. (University Of Romania)
[11]  Ashwani K. Rana, Narottam Chand and Vinod Kapoor, "Gate Current Modeling and Optimization of High-k Gate Stack MOSFET Structure in Nano Scale Regime, " International Journal of Micro-Nano Scale Transport, Vol. 1, No. 3, pp. 253-267, 2010. (Multi-Science Publishing Company)
[12]  Ashwani K. Rana and S.Dasgupta, "Unified Compact Modeling of a gate Tunneling Current considering Image Force Induced Barrier Lowering for a nanoscale N-MOSFET, " Journal of Computational and Theoretical Nanoscience (JCTN), Vol. 4, No. 3, pp. 482-487, 2007.(ASP)
[13]  Ashwani K. Rana and S.Dasgupta, "Gate Leakage Power analysis for a Nanoscale N-MOSFET, " Journal of Computational and Theoretical Nanoscience (JCTN), Vol. 5, No. 11, pp. 2180-2185, Nov 2008.(ASP)
[14]  Ashwani K. Rana, Shashi B. Rana Anjna Kumari, Vaishnav Kiran, "Significance of Nanotechnology in construction Engineering." International Journal of Recent trends in Engineering, Vol. 1, No. 4, pp. 46-48, May 2009.
[15]  Ashwani K. Rana, Narottam Chand and Vinod Kapoor, "Trap Assisted Tunneling Model for Gate Current in Nano Scale MOSFET with High-K Gate Dielectrics, International Journal of Electrical and Electronics Engineering, Vol. 3, No. 7, pp. 402-409, 2009. World Academy of Science and Engineering Technology) (WASET)
[16]  Ashwani K. Rana, Narottam Chand and Vinod Kapoor, "Analysis and Application of Hybrid MOSFET Structure for Low Gate Leakage, " Journal of Engineering and Applied Science, Vol. 6, No. 1, pp. 38-46, 2011. (Medwell Journals)
[17]  Neha Sharan and Ashwani K. Rana, " Impact of Strain and Channel Thickness on Performance of Biaxial Strained Silicon MOSFETS, " International Journal of VLSI design & Communication Systems (VLSICS), Vol. 2, No. 1, pp. 61-71, March 2011.
[18]  Neha Sharan and Ashwani K. Rana, "Performance Evaluation of Strained Channel NMOS in Nano Regime, " International Journal of Micro and Nano Systems, Vol. 2, No. 1, pp. 53-58, 2011.
[19]  Neha Sharan and Ashwani K. Rana, "Analysis of VLSI Circuits Designed with Single and Dual Channel Strained Silicon MOSFETS in Nanoregime, " Journal of VLSI Design Tools & Technology, Vol. 1, No. 1, 2011.
[20]  Deepesh Ranka, Ashwani K. Rana, Rakesh Kumar Yadav, Kamalesh Yadav and Devendra Giri, " Performance Evaluation of FD-SOI MOSFETS for Different Metal Gate Work Function, " International Journal of VLSI design & Communication Systems (VLSICS), Vol. 2, No.1, March 2011.
[21]  Deepesh Ranka, Ashwani K. Rana, Rakesh Kumar Yadav and Devendra Giri, "Performance Analysis of FD-SOI MOSFET with Different Gate Spacer Dielectric, " International Journal of Computer Applications, Vol. 18, No. 5, pp. 22-27, March 2011.
[22]  Gaurav Saini and Ashwani K. Rana, "Physical Scaling Limits of FinFET Structure: A Simulation Study, " International Journal of VLSI design & Communication Systems (VLSICS), Vol. 2, No. 1, pp. 26-35, March 2011.
[23]  Ashwani K. Rana, Anjna Kumari, Vaishnav Kiran and Sanjay Jamwal, "Implication of Nanotechnology application on Environment." IETE Journal of Education, Vol 50, Issue 1, pp 25-36, Jan-April, 2009.

Publications: Conferences/Workshops/Symposiums

[1]  Ashwani K. Rana, S. Dasgupta, "Impact of Image Force Induced Barrier Lowering on the Analytical Modeling of a Gate Leakage Current for a N-MOSFET in Nanoscale Regime, " International Conference on Recent Trends in Nano Science and Technology (ICRTNT)-, Jadavpur university, Kolkatta, India, pp. 282-285, Dec-7-9, 2006.
[2]  Ashwani K. Rana, Surender Soni and Ashok Kumar, "Effect of Inductance on Wire Sizing the Global Interconnect in VLSI Circuits, " 11th IEEE VLSI Design and Test Symposium (VDAT-07), Saha Institute of Nuclear Physics Convention Centre, Salt Lake Kolkata, India, August 8-11, 2007.
[3]  Ashwani K. Rana, Vinod Kapoor and Narottam Chand, "A New Role for the Teacher of the Future in Technical Education, " International conference on Active teaching & learning in Higher Education, ICFAI National College, pp. 105-108, Dec 8-9, 2007.
[4]  Neerav Mehan, Ashwani K. Rana and Surender Soni, " An optimized CMOS Dynamic comparator with improved accuracy for high performance ADC’s , International conference on Emerging Trends in Signal Processing and VLSI Design, Guru Nanak Engineering College Convention Centre, Hyderabad, 11-13th June, 2010.
[5]  Pankaj K. Pal and Ashwani K. Rana, "New Low power technique: Leakage feedback with stack and sleepy stack with keeper", IEEE International conference on computer & communication Technology (ICCCT-2010), MNIT Allahabad, pp. 296-301, 17-19 Sept 2010.
[6]  Ashwani K. Rana, Narottam Chand and Vinod Kapoor, "TCAD Based Analysis of Gate Leakage Current for High-k Gate Stack MOSFET, " International Conference on Advances in Electrical & Electronics, Thiruvananthapuram, Kerala, India, Dec 21-22, pp 114-117, Dec 2010.
[7]  Rakesh Kumar Yadav, Deepesh Ranka, Kamalesh Yadav and Ashwani K. Rana, " A CMOS Buffer without Short Circuit Power Consumption for Low Power Application, " International Conference on Advances in Electrical & Electronics, Thiruvananthapuram, Kerala, India, Dec 21-22, pp 212-215, Dec 2010.
[8]  Gaurav Saini, Ashwani K. Rana, Pankaj Pal and Sunil Jadav, "Leakage Behavior of Underlap FinFET Structure: A Simulation Study, " IEEE International conference on computer & communication Technology (ICCCT-2010), MNIT Allahabad, pp. 302-305, 17-19 Sept 2010.
[9]  Neha Sharan and Ashwani K. Rana, "Performance modeling of strained silicon MOSFET, " International conference on Advances in communication, Embedded Systems and Computing (ICACEC), January 14-15, SIRT Bhopal, pp. 540-545, 2011.
[10]  Neha Sharan and Ashwani K. Rana, "Analysis of uniaxial strained silicon MOSFET Performance, " Innovative conference on Embedded Systems, Mobile Communication and Computing (ICEMC2), August 6-8, Bengaluru, 2011.
[11]  Deepesh Ranka, Ashwani K. Rana, Rakesh Kumar Yadav and Kamalesh Yadav, "Comparative performance Evaluation of Bulk and FD-SOI MOSFET using TCAD, " International conference on Devices and Communication(ICDeCom), BIT, Mesra, Ranchi, Jharkhand, India, pp. 1-5, Feb 2011(IEEE Xplore).
[12]  Deepesh Ranka, Ashwani K. Rana , Rakesh Kumar Yadav , Kamalesh Yadav, "Performance Assessment of FD-SOI MOSFET Using TCAD Simulations, " International Conference on Advances in Computing and Communication (ICACC’2011), NIT, Hamirpur, Himachal Pradesh, INDIA, pp. 309-312, April 8-10, 2011.
[13]  Deepesh Ranka, Ashwani K. Rana , Rakesh Kumar Yadav , Kamalesh Yadav, " Impact of metal gate work function on the performance of Fully depleted SOI MOSFET, International conference on Advances in communication, Embedded Systems and Computing (ICACEC), January 14-15, SIRT Bhopal, 2011.
[14]  Rakesh Kumar Yadav, Ashwani K. Rana, Shweta Chauhan, Deepesh Ranka and Kamalesh Yadav, " Four Phase Clocking Rule for Energy Efficient Digital Circuit- An Adiabatic Concept, " IEEE International conference on Computer and Communication Technology (ICCCT-11), pp. 209-214, Sep, 2011.
[15]  Rakesh Kumar Yadav, Ashwani K. Rana, Shweta Chauhan, Deepesh Ranka and Kamalesh Yadav, "Adiabatic Technique for Energy Efficient Logic Circuit Design, " IEEE International conference on Emerging Trends in Electrical and Computer Technology(ICETECT), Kanyakumari, Tamil Nadu, India, pp. 776-780, 23-24 March 2011. (IEEE Xplore)
[16]  Rakesh Kumar Yadav, Ashwani K. Rana, Shweta Chauhan, Deepesh Ranka and Kamalesh Yadav, " Performance Evaluation of Adiabatic Logic Circuit for Low Power Application, " International conference on Computer, Communication and Electrical Technology (ICCCET-2011), Maruthakulam, Tirunelveli, Tamilnadu, India, pp. 301-307, 18-19 March 2011. (IEEE Xplore)
[17]  Saurabh sharma, Ashwani K. Rana, Manoj Kumar Bansal, " Optimization of MCML Unit cell in 100 NM Technology, " International Conference on Advances in Computing and Communication (ICACC-2011), NIT, Hamirpur (Himachal Pradesh), INDIA, pp. 301-307. April 8-10, 2011.
[18]  Gaurav Saini, Ashwani K Rana, Manoj Kumar, "SOI versus Double Gate FinFET: A Comparative Simulation Study, " International Conference on Advances in Computing and Communication (ICACC’2011) NIT Hamirpur, Himachal Pradesh, INDIA, pp. 351-353April 8-10, 2011.
[19]  Rakhi Puri and Ashwani K. Rana, "Comparative Study of VLSI Switches." Emerging Trends in Computing and Communication (ETCC-2007), National Institute of Technology, Hamirpur, India, July 27-28, 2007.
[20]  Ashwani K. Rana, Vinod Kapoor, Narottam Chand and S.Dasgupta, "The Future of VLSI: A Survey of Nano-electronics." Emerging Trends in Computing and Communication (ETCC-2007), National Institute of Technology, Hamirpur, India, July 27-28, 2007.
[21]  Ashwani K. Rana, "Nanotechnology-Safety Aspect." Trends in VLSI and Embedded System (IMS-07), Punjab Engineering College, Chandigarh, India, pp. 361-366, August 17-18, 2007.
[22]  Ashwani K. Rana, Anil Sharma, Ashok Kumar, Hitesh K. Dhiman, Senthil K. and Vijay Bhushan, " Modeling Gate Tunneling Current for Nanoscale N-MOSFET Analytically." Trends in VLSI and Embedded System (IMS-07), Punjab Engineering College, Chandigarh, India, pp. 37-41, August 17-18, 2007.
[23]  Ashwani K. Rana, Abhishek Tondon, Sandeep, Prakash and Sanchit Sharma, " 8 BIT PROCESSOR-FPGA BASED DESIGN, " National Conference on VLSI and Communication (NC-VCOM-08), SAINTGITS College of Engineering, Kottayam, KERALA, March 14-15, 2008
[24]  Ashwani K. Rana, Vaishnav Kiran and Anjna Jamwal, "VLSI System Design Challenges in Nanoscale Regime, " National Conference on VLSI and Communication (NC-VCOM-08), SAINTGITS College of Engineering, Kottayam, KERALA, March 14-15, 2008
[25]  Sandeep Kumar and Ashwani K. Rana, "Review and Future Direction for MOSFET Gate Dielectric Materials for Integrated Circuit Applications, " Recent Advances in Materials (RAIM-08), National Institute of Technology, Hamirpur, India, Feb 16-17, 2008
[26]  Abhishek Tondon and Ashwani K. Rana, "Wideband Semiconductor Materials for High Temperature Applications: A Comprehensive Review, " Recent Advances in Materials (RAIM-08), National Institute of Technology, Hamirpur, India, Feb 16-17, 2008
[27]  Ashwani K. Rana, Anjna Kumari and Vaishnav Kiran, "Semiconductor Materials for Organic Transistors, " Recent Advances in Materials (RAIM-08), National Institute of Technology, Hamirpur, India, Feb 16-17, 2008.
[28]  Abhishek Tondon, Sandeep Kumar and Ashwani K. Rana, "Role of Electronic sensors in Civil Engineering: Developments and Prospects, National Conference on Infrastructure Development in Civil Engineering (IDCE-2008), National Institute of Technology, Hamirpur, India, May 16-17, 2008
[29]  Ashwani K. Rana, Anjna Kumari and Vaishnav Kiran, "NANOTECHNOLOGY – SOCIETAL AWARENESS AND APPLICATIONS, " National Conference on Nanotechnology and its Applications in Quantum Computing-(NAQC-2008), Government College of Engineering and Leather Technology, Kolkata, West Bengal, India, Sept 22-24, 2008.
[30]  Abhishek Tondon and Ashwani K. Rana, "CMOS Transmission Gates: Performance Variation Trends and Comparison with Static CMOS Logic, " National Conference on Architecturing Future IT Systems (NCAFIS’ 08), DEVI AHILYA UNIVERSITY, Indore (MP)-October 17-18 2008
[31]  Ashwani K. Rana, Naresh Kumar and Vinod Kapoor, "MEMS Packaging- Material Requirement and Reliability Issues, " National conference on Mechanism Science and Technologies: From theory to Application (NCMSTA-08), National Institute of Technology, Hamirpur, India, pp. 718-724, Nov 13-14, 2008.
[32]  Naresh Kumar, Ashwani K. Rana, Vinod Kapoor and Narrottam Chand, "Spintronics- A Bright Future for Electronics." National conference on Recent advances in Electrical Engineering (RAEE-2008), Dec 26-27, 2008, EED, NIT Hamirpur.
[33]  Ashwani K. Rana, Vinod Kapoor and Narottam Chand, "Wireless Sensor/Actuator networks: Opportunities and Challenges." National Conference on wireless and Optical Communication (WOC-08)-2008, PEC Chandigarh (Deemed University), pp 69-75, Dec 18-19, 2008, .
[34]  Shashi B. Rana, Ashwani K Rana and Chintan Julka, "Core to 4G Communication--Open Wireless Architecture." National Conference on Emerging Trends in Computing and Communication (ETCC-2008), NIT Hamirpur, pp 212-215, Dec 30-31, 2008
[35]  Ashwani Kumar Rana, Gaurav Saini, Sunil Jadav, Manoj Kumar Vinod kapoor and Narottam Chand, "Recent advances in High Resolution Lithography for VLSI Application." National Conference on Emerging Trends in Computing and Communication (ETCC-2008), NIT Hamirpur, pp 363-368, Dec 30-31, 2008
[36]  Ashwani K. Rana, Shashi B. Rana, "Role of Nanotechnology for Future Wireless Devices and Communications, " DAV Jalandher, (NCOW-08), Nov 27-28 2008, pp 36-40.
[37]  Ashwani K. Rana, Vaishnav Kiran, Anjna Kumari and Bandna Kumari, "Recent advances in organic Polymer for electronics in Nano regime." National Conference on Emerging Trends in Computing and Communication (ETCC-2008), NIT Hamirpur, pp 338-342, Dec 30-31, 2008
[38]  Ashwani Kumar Rana, Sandeep Kumar, Sanchit Sharma and Shashi B. Rana, "Comparative Study of Logic Circuits Using CMOS and BICMOS Technology for VLSI Application, " Cutting Edge Computer and Electronics technologies (CECET-2009), GB Pant Nagar, pp 365-369 Feb, 2009.
[39]  Ashwani K. Rana, Naresh Kumar, Ajay Sharma and Vinod Kapoor, "Radio over Fiber Networks: Perspectives and Challenges." National Conference on Next Generation Computing and Information Systems, NGCIS ’09, Feb 14-15, Model Institute of Engineering and Technology, Jammu, pp 218-220, 2009.