Electrical and Electronic Engineering

Electrical and Electronic Engineering is an open access journal that provides rapid publication of articles in all areas of the subject. The journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence.

Tze-Yun Sung

Editorial Board Member of Electrical and Electronic Engineering

Professor, Department of Electronics Engineering, Chung Hua University, Taiwan

Research Areas

VLSI Signal Processing, System On Chip (Soc), Embedded System Design, Image Processing, Computer Graphics, Communication Systems, High Performance DSP Architecture and Digital Arithmetic.

Education

1987Ph.DNational Taiwan University

Experience

2008-presentprofessor with the Department of Electronics Engineering, Chung Hua University, Hsinchu City, Taiwan
2005-2008Professor and Chairman with the Department of Microelectronics Engineering, Chung Hua University, Hsinchu City, Taiwan
1992Department of Electrical Engineering, Chung Hua University, Hsinchu City, Taiwan
1989-1992Chief Researcher with the Telecommunication Laboratory, Department of Transportation and Communication, Taoyuan, Taiwan
1979-1989Associate Researcher and project leader with the Division of Electronics, Chung Shan Institute of Science and Technology, Department of Defense, Taoyuan, Taiwan

Membership

IEICE
IEEE

Publications: Journals

[1]  Tze-Yun Sung, Chen-Tang Cheng, "Design and Implementation of 16-bit General Purpose Microcontroller", The Chung Hua Journal of Science and Engineering, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.1, No.1, March 2003, pp. 29-36.
[2]  Tze-Yun Sung, Yi-Hsun Sung, "Numerical Accuracy and Hardware Trade-offs for CORDIC Arithmetic for DSP Applications, " The Chung Hua Journal of Science and Engineering, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.2, No.1, March 2004, pp. 24-31.
[3]  Tze-Yun Sung, Chich-Sin Chen, "Design and Implementation of a 1024-Point FFT Processor Using Memory Interleaving, " The Chung Hua Journal of Science and Engineering, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.2, No. 1, March 2004, pp. 16-23.
[4]  Tze-Yun Sung, Chich-Sin Chen, Yi-Hsun Sung, "The Algorithms of Color Spaces and Image Dithering for Flat Panel Display Controller for VLSI Implementation, " The Chung Hua Journal of Science and Engineering, College of Engineering, Chung Hua University, Hsin-chu, Taiwan, Vol.2, No. 2, June 2004, pp.87-94.
[5]  Tze-Yun Sung, Chich-Sin Chen, Ming-Chou Shih, Kuo-Jen Lin, "Design of a High-Speed Sine and Cosine Generator Based on Double-Rotation CORDIC Algorithm in OFDM System, " The Chung Hua Journal of Science and Engineering, Special Issue on Information Systems and Applications for Next Generation, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.3, No.1, Jan. 2005, pp.19-26.
[6]  Tze-Yun Sung, Kuo-Jen Lin, "The Quantization Effects of CORDIC Arithmetic with Expanding the Convergence Range, " The Chung Hua Journal of Science and Engineering, School of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.3, No.3, May 2005, pp.39-46.
[7]  Tze-Yun Sung, Chih-Sin Chen, Ming-Chou Shih, "FPGA Implementation of a High-Speed CORDIC-Based Sine and Cosine Generator for OFDM Systems, " The Chung Hua Journal of Science and Engineering, College of Engineering, Chung Hua University, Hsin-chu, Taiwan, Vol.3, No.3, May 2005, pp.47-54.
[8]  Tze-Yun Sung, Chich-Sin Chen, "An Efficient 8×8 2-D DCT,IDCT Core Processor for Image Data Compression, " The Chung Hua Journal of Science and Engineering, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.3, No.3, May 2005, pp.79-86.
[9]  Tze-Yun Sung, "A Parallel and Pipelined Architecture for Fast Three-Dimensional Rotation Using Double Rotation CORDIC Algorithm in Graphic Engine, " The Chung Hua Journal of Science and Engineering, Special Issue on Applied Mathematics, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.3, No.4, July 2005, pp.69-79.
[10]  Tze-Yun Sung, "Two Fast Architectures for Two-Dimensional Discrete Wavelet Transform and Its Inversion Using Direct Form, " The Chung Hua Journal of Science and Engineering, Special Issue on Applied Mathematics, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.3, No.4, July 2005, pp.113-123.
[11]  Tze-Yun Sung, Yaw-Shih Shieh, Kuo-Jen Lin, Cheui-Lu Chiu, "Area, Power and Throughput Trade-Offs in the Design of Pipelined 2-D Discrete Wavelet Transform Architectures Using Direct Cascading Form", The Chung Hua Journal of Science and Engineering, Special Issue on Electrical Engineering, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.3, No.5, Sept. 2005, pp.3-10.
[12]  Kuo-Jen Lin, Chen-Yu Wu, Tze-Yun Sung, Yaw-Shih Shieh, "A High Speed and Low Dead Zone PFD with Delay Circuits, " The Chung Hua Journal of Science and Engineering, Special Issue on Electrical Engineering, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.3, No.5, Sept. 2005, pp.137-141.
[13]  Tze-Yun Sung, Ming-Chou Shih,, Chich-Sin Chen, "A Novel Implementation of High-Throughput 3-D Rotation and Perspective for Graphic Engine, " The Chung Hua Journal of Science and Engineering, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.3, No.6, Dec. 2005, pp.11-17.
[14]  Tze-Yun Sung, Yaw-Shih Shieh, "A High-Speed,Ultra Low-Power Architecture for Two-Dimensional Discrete Wavelet Transform, " The Chung Hua Journal of Science and Engineering, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.3, No.6, Dec. 2005, pp.38-45.
[15]  Tze-Yun Sung, Ming-Chou Shih,, Chich-Sin Chen, "FPGA Implementation of High-Speed 3-D Graphic Engine Using Double Rotation CORDIC Algorithm, " The Chung Hua Journal of Science and Engineering, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.3, No.6, Dec. 2005, pp.73-78.
[16]  Tze-Yun Sung, Yaw-Shih Shieh, "A High-Speed/Low-Power Architecture for Two-Dimensional Inverse Discrete Wavelet Transform With Multiplierless Operation, " The Chung Hua Journal of Science and Engineering, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.3, No.6, Dec. 2005, pp. 112-119.
[17]  Tze-Yun Sung, "Memory-Efficient and High-Speed Split-Radix FFT/IFFT Processor Based on Pipelined CORDIC Rotations, " IEE Proc.-Vis. Image Signal Process., Vol. 153, No. 4, Aug., 2006, pp. 405-410. (SCI)
[18]  Tze-Yun Sung, Yaw-Shih Shieh, "VLSI Implementation of A High-Efficient and Cost-Effective LCD Signal Processor, " The Chung Hua Journal of Science and Engineering, Special Issue on Applied Mathematics and Microelectronics Engineering, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.4, No.3, Sep. 2006, pp.77-82.
[19]  Jyun-Hong Chen, Yaw-Shih Shieh, Tze-Yun Sung, "The Closed-loop Control for Dual-Output Boost Converter with Single Inductor, " The Chung Hua Journal of Science and Engineering, Special Issue on Applied Mathematics and Microelectronics Engineering, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.4, No.3, Sep. 2006, pp.83-90.
[20]  Tze-Yun Sung, Yaw-Shih Shieh, Hsi-Chin Hsin, "Memory-Efficient and Fast Architectures for Forward and Inverse DCT with Multiplierless Operation, " The Chung Hua Journal of Science and Engineering, Special Issue on Electrical Engineering, College of Engineering, Chung Hua University, Hsinchu, Taiwan, Vol.4, No.4, Dec. 2006, pp.23-28.
[21]  Tze-Yun Sung, Hsi-Chin Hsin, "Design and Simulation of Reusable IP CORDIC Core for Special-Purpose Processors, " to appear in IEE Proc.-Comput. Digit. Tech.. (SCI)
[22]  Tze-Yun Sung, Hsi-Chin Hsin, "Fixed-Point Error Analysis of CORDIC Arithmetic for Special-Purpose Signal Processors, " to submit to IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. (SCI)
[23]  Tze-Yun Sung, Hsi-Chin Hsin, "An Efficient Rearrangement of Wavelet Packet Coefficients for Embedded Image Coding Based on SPIHT Algorithm, ' to submit to IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. (SCI)
[24]  Tze-Yun Sung, Hsi-Chin Hsin, "Fast and Memory-Efficient Architectures for Two-Dimensional DCT and IDCT Based on Constant-Rotation CORDIC, " to submit to IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on "VLSI Design and CAD Algorithm". (SCI)
[25]  Tze-Yun Sung, "FPGA Implementation of Reconfigurable CORDIC Core for Special-Purpose Processors, " to submit to IEICE Transactions on Information and Systems, Special Section on "Reconfigurable Systems". (SCI)

Publications: Conferences/Workshops/Symposiums

[1]  Tze-Yun Sung, Yung-Tsung Chen, Chich-Sin Chen, "Image Processing Algorithms Applying on Flat Panel Display Controller", 2003 Computer Graphics Workshop, Tong-Hua University, Hualian, Taiwan, August, 28~29, 2003.
[2]  Tze-Yun Sung, Yung-Tsung Chen, Yi-Hsun Sung, "HDL Implementation of Optimal Image Scaling Algorithm for Flat Panel Display", The 14th Workshop on Object-Orient Technology and Applications, Yuan-Ze University, Chungli, Taiwan, Sept. 12, 2003.
[3]  Tze-Yun Sung, Chich-Sin Chen, Yi-Hsun Sung, "Implementation of Image Processing Algorithms for Flat Panel Display Using Hardware Description Language", The 14th Workshop on Object-Orient Technology and Applications, Yuan-Ze University, Chungli, Taiwan, Sept. 12, 2003.
[4]  Tze-Yun Sung, "Design and Implementation of 16-bit General Purpose Microcontroller-CH*MCU-16", 2003 Workshop on Consumer Electronics, Cheng-Kung University, Tainan, Taiwan, Nov. 27~28, 2003.
[5]  Tze-Yun Sung, Jian-Min Lin, "Design and Implementation Of Enriched Instruction Set 8051 Microcontroller-CH*MCU-R251", 2003 Workshop on Consumer Electronics, Cheng-Kung University, Tainan, Taiwan, Nov. 27~28, 2003.
[6]  Tze-Yun Sung, Chich-Sin Chen, Yi-Hsun Sung, "Chip Implementation of Image Processing Algorithms for Flat Panel Display Controller-F*Con-V.1", 2003 Workshop on Consumer Electronics, Cheng-Kung University, Tainan, Taiwan, Nov. 27~28, 2003.
[7]  Tze-Yun Sung, Yung-Tsung Chen, Yi-Hsun Sung, "Chip Implementation of Optimal Image Scaling Algorithm for Flat Panel Display Controller-F*Con-V.1", 2003 Workshop on Consumer Electronics, Cheng-Kung University, Tainan, Taiwan, Nov. 27~28, 2003.
[8]  Tze-Yun Sung, Yung-Tsung Chen, Chich-Sin Chen, Yi-Hsun Sung, "Chip Implementation of Image Processing Algorithms for Flat Panel Display Controller F*Con-V.1", 2003 National Computer Symposium, Feng-Chia University, Taichung, Taiwan, Dec. 18~19, 2003.
[9]  Tze-Yun Sung, "A Parallel-Pipelined Constant Geometry Algorithm (PCGA) for Computation of FFT on a Special Processor", The 21st Workshop on Combinatorial Mathematics and Computation Theory, Taichung Healthcare and Management University, Taichung, Taiwan, May 21~22, 2004, pp. 218-227.
[10]  Tze-Yun Sung, Yi-Hsun Sung, Chich-Sin Chen, " An Efficient Parallel-Pipelined Algorithm and Architecture for Computation of 2-D DCT on Two Successive Processors", The 21st Workshop on Combinatorial Mathematics and Computation Theory, Taichung Healthcare and Management University, Taichung, Taiwan, May 21~22, 2004, pp. 200-207.
[11]  Tze-Yun Sung, Yi-Hsun Sung, "The Quantization Effects of CORDIC Arithmetic for Digital Signal Processing Applications", The 21st Workshop on Combinatorial Mathematics and Computation Theory, Taichung Healthcare and Management University, Taichung, Taiwan, May 21~22, 2004, pp. 16-25.
[12]  Tze-Yun Sung, Chich-Sin Chen, Yi-Hsun Sung, "A Cost-Effective 1024-Point FFT Processor', 2004 Conference on Electronic Communication and Applications, Su-Te University, Kaohsiung, Taiwan, May 28, 2004.
[13]  Tze-Yun Sung, Chich-Sin Chen, "An Efficient 8×8 2-D DCT Core Processor for Image Data Compression", 2004 Conference on Electronic Communication and Applications, Su-Te University, Kaohsiung, Taiwan, May 28, 2004.
[14]  Tze-Yun Sung, Ming-Chou Shih, Chich-Sin Chen, Yi-Hsun Sung, "An Efficient 8×8 2-D DCT,IDCT Core Processor for Image Data Compression", 2004 Symposium of Digital Life and Internet Technologies, Cheng-Kung University, Tainan, Taiwan, June 24~26, 2004, pp.202-205.
[15]  Tze-Yun Sung, Chich-Sin Chen, "A Parallel-Pipelined Processor for Fast Fourier Transform, " The Fourth IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC) 2004, Fukuoka, Japan, August 3-5, 2004, pp.194-197(10-1). (EI)
[16]  Tze-Yun Sung, Yi-Hsun Sung, "A Novel Implementation of Cost-Effective Parallel-Pipelined 8×8 DCT Processor, " The Fourth IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC) 2004, Fukuoka, Japan, August 3-5, 2004, pp.200-203(10-3). (EI)
[17]  Tze-Yun Sung, Chich-Sin Chen, Yi-Hsun Sung, Ming-Chou Shih, "A Novel VLSI Implementation of 8×8 2-D DCT/IDCT Core Processor for Image Data Compression, " 2004 Computer vision, Graphic and Image Processing Conference (CVGIP-2004), Hualian, Taiwan, August 15-17, 2004, P1-14.
[18]  Tze-Yun Sung, Yung-Tsung Chen, Yi-Hsun Sung, "A Memory-Efficient and High-Speed Split-radix FFT/IFFT Processor Based on Pipelined CORDIC Rotations, " 2004 Workshop on Consumer Electronics and Signal Processing (WCEsp-2004), Chiao Tung University, Hsinchu, Taiwan, Nov. 17-18, 2004, Oral 9-4.
[19]  Tze-Yun Sung, Chich-Sin Chen, Ming-Chou Shih, "Double Rotation CORDIC: A Novel Algorithm for Fast Sine/Cosine Generation, " 2004 Workshop on Consumer Electronics and Signal Processing (WCEsp-2004), Chiao Tung University, Hsinchu, Taiwan, Nov. 17-18, 2004, Oral 9-1.
[20]  Tze-Yun Sung, Chich-Sin Chen, Ming-Chou Shih, " Fast CORDIC-Based Sine/Cosine Generator Using a Double Rotation Algorithm and a Novel-prediction Algorithm, " 2004 National Symposium on Telecommunications, National Taiwan Ocean University, Keelung, Taiwan, Dec. 3-4, 2004, DSP-2-2.
[21]  Tze-Yun Sung, Yung-Tsung Chen, Yi-Hsun Sung, "A Memory-Efficient and High-Speed FFT/IFFT Processor for OFDM Systems, " 2004 National Symposium on Telecommunications, National Taiwan Ocean University, Keelung, Taiwan, Dec. 3-4, 2004, DSP-1-1.
[22]  Tze-Yun Sung, Chich-Sin Chen, "Implementation of Color Image Processing Algorithms for LCD Monitor Controller, " First Science and Technology Conference-Photonics and Communications, National Kaohsiung University of Applied Sciences, Kaohsiung, Taiwan, Dec. 9-10, 2004, A-04.
[23]  Tze-Yun Sung, Yung-Tsung Chen, "Implementation of Optimal Image Scaling Algorithm for LCD Monitor Controller, " First Science and Technology Conference-Photonics and Communications, National Kaohsiung University of Applied Sciences, Kaohsiung, Taiwan, Dec. 9-10, 2004, PJ-01.
[24]  Tze-Yun Sung, Ming-Chou Shih, Chich-Sin Chen, "A Low-Latency CORDIC-Based Sine and Cosine Generator for OFDM System, " First Science and Technology Conference-Photonics and Communications, National Kaohsiung University of Applied Sciences, Kaohsiung, Taiwan, Dec. 9-10, 2004, QK-10.
[25]  Tze-Yun Sung, Yung-Tsung Chen, "A Memory-Efficient and High-Speed CORDIC-Based Split-radix FFT Processor for OFDM System, " First Science and Technology Conference-Photonics and Communications, National Kaohsiung University of Applied Sciences, Kaohsiung, Taiwan, Dec. 9-10, 2004, QK-05.
[26]  Tze-Yun Sung, Chich-Sin Chen, Ming-Chou Shih, "The Double Rotation CORDIC Algorithm: New Results for VLSI Implementation of Fast Sine/Cosine Generation, " 2004 International Computer Symposium (ICS-2004), Taipei, Taiwain, Dec. 15-17, 2004, pp.1285-1290. (EI)
[27]  Tze-Yun Sung, Chich-Sin Chen, Ming-Chou Shih, "FPGA Implementation of 3-D Graphic Engine Using Double Rotation CORDIC Algorithm, " 2005 IEEE International Conference on Systems and Signals (ICSS-2005), I-Shou University, Kaohsiung, Taiwan, April 28-29, 2005, pp.532-536. (EI)
[28]  Tze-Yun Sung, Ming-Chou Shih, Chich-Sin Chen, "A Novel Implementation of High-Throughput 3-D Rotation and Perspective for Graphic Engine, " 2005 IEEE International Conference on Systems and Signals (ICSS-2005), I-Shou University, Kaohsiung, Taiwan, April 28-29, 2005, pp.707-711. (EI)
[29]  Tze-Yun Sung, Chich-Sin Chen, Ming-Chou Shih, "FPGA Implementation of a High-Speed CORDIC-Based Sine and Cosine Generator for OFDM Systems, " 2005 IEEE International Conference on Systems and Signals (ICSS-2005), I-Shou University, Kaohsiung, Taiwan, April 28-29, 2005, pp.1105-1109. (EI)
[30]  Tze-Yun Sung, Yaw-Shih Shieh, "An Efficient Architecture for 2-D Inverse Discrete Wavelet Transform with Multiplierless Operation, " 2005 IEEE International Conference on Systems and Signals (ICSS-2005), I-Shou University, Kaohsiung, Taiwan, April 28-29, 2005, pp.332-337. (EI)
[31]  Tze-Yun Sung, Yaw-Shih Shieh, "A High-Speed/Ultra Low-Power Architecture for 2-D Discrete Wavelet Transform, " 2005 IEEE International Conference on Systems and Signals (ICSS-2005), I-Shou University, Kaohsiung, Taiwan, April 28-29, 2005, pp.326-331. (EI)
[32]  Tze-Yun Sung, Yaw-Shih Shieh, "A High-Speed and Low-power Architecture for 2-D Inverse Discrete Wavelet Transform with Multiplierless Operation, " 2005 Conference on Microelectronics Technology and Applications (2005-CMTA), National Kaohsiung Marine University, Kaohsiung, Taiwan, May 20, 2005, D-2.
[33]  Tze-Yun Sung, Yaw-Shih Shieh, "A High-Speed and Low-Power Architecture for 2-D Discrete Wavelet Transform in Image Data Compression System, " 2005 Conference on Microelectronics Technology and Applications (2005-CMTA), National Kaohsiung Marine University, Kaohsiung, Taiwan, May 20, 2005, D-3.
[34]  Tze-Yun Sung, Chih-Sin Chen, Ming-Chou Shih, "Novel VLSI Implementation of a High-Speed CORDIC-Based Sine and Cosine Generator for OFDM Systems, " 2005 Conference on Microelectronics Technology and Applications (2005-CMTA), National Kaohsiung Marine University, Kaohsiung, Taiwan, May 20, 2005, D-4.
[35]  Tze-Yun Sung, Chih-Sin Chen, "A Novel VLSI Implementation of High-Throughput 3-D Rotation for Graphic Engine Using Double Rotation CORDIC Algorithm, " 2005 Conference on Microelectronics Technology and Applications (2005-CMTA), National Kaohsiung Marine University, Kaohsiung, Taiwan, May 20, 2005, D-5.
[36]  Tze-Yun Sung, Chih-Sin Chen, "A High-Efficiency Architecture for 3-D Rotation Using Fast CORDIC Algorithm in Graphic Engine, " 2005 Symposium on Digital Life and Internet Technologies (Credit-2005), National Cheng-Kung University, Tainan, Taiwan, June 2-3, 2005, 2A-4.
[37]  Tze-Yun Sung, Yaw-Shih Shieh, "Analysis and Implementation of Pipelining Architectures for 2-D Discrete Wavelet Transform and Its Inversion Using Direct Cascading Form, " 2005 Symposium on Digital Life and Internet Technologies(Credit-2005), National Cheng-Kung University, Tainan, Taiwan, June 2-3, 2005, 2A-5.
[38]  Tze-Yun Sung, Yaw-Shih Shieh, Kuo-Jen Lin, Cheui-Lu Chiu, "Area and Throughput Trade-offs in The Design of Pipelined 2-D Discrete Wavelet Transform Architectures, " 2005 Computer vision, Graphic and Image Processing Conference (CVGIP-2005), Taipei, Taiwan, August 21-23, 2005, pp.370-377.
[39]  Tze-Yun Sung, Chih-Sin Chen, Yaw-Shih Shieh, Kuo-Jen Lin, "Design and Implementation of LCD Monitor/TV Signal Processor, " 2005 Computer vision, Graphic and Image Processing Conference (CVGIP-2005), Taipei, Taiwan, August 21-23, 2005, pp.364-369.
[40]  Tze-Yun Sung, Chih-Sin Chen, Yaw-Shih Shieh, Kuo-Jen Lin, "Hardware Implementation of Fast 3-D Rotation Using Double Rotation CORDIC Algorithm in Graphic Engine, " 2005 Computer vision, Graphic and Image Processing Conference (CVGIP-2005), Taipei, Taiwan, August 21-23, 2005, pp.1362-1370.
[41]  Tze-Yun Sung, Chih-Sin Chen, Yaw-Shih Shieh, Kuo-Jen Lin, "Design and Analysis of a High-Speed Sine/Cosine Generator in OFDM System, " 2005 Active Networking Workshop (ANW-2005), Yuan-Ze University, Chungli, Taiwan, September 2, 2005, 1B-5.
[42]  Tze-Yun Sung, Yaw-Shih Shieh, Kuo-Jen Lin, Chun-Wang Yu, "FPGA Implementation of Image Scalar for LCD Monitor and TV Controller, " 2005 Workshop on Consumer Electronics and Signal Processing (WCEsp-2005), Yunlin University of Science and Technology, Yunlin, Taiwan, Nov. 17-18, 2005, 2-3.
[43]  Tze-Yun Sung, Yaw-Shih Shieh, Kuo-Jen Lin, Cheui-Lu Chiu, "Area, Power and Throughput Trade-Offs for 2-D Inverse Discrete Wavelet Transform Architectures Using Direct Form, " 2005 Workshop on Consumer Electronics and Signal Processing (WCEsp-2005), Yunlin University of Science and Technology, Yunlin, Taiwan, Nov. 17-18, 2005, 4-18.
[44]  Tze-Yun Sung, Yaw-Shih Shieh, Kuo-Jen Lin, "VLSI Implementation of a Memory-Efficient and High-Speed Split-Radix FFT/IFFT Processor for Wireless LAN, " 2005 Asia Pacific Symposium on EMC (APEMC-2005), Taipei, Taiwan, Dec.6-9, 2005, pp.428-431. (EI)
[45]  Tze-Yun Sung, Yaw-Shih Shieh, Kuo-Jen Lin, Cheui-Lu Chiu, "VLSI Implementation of Pipelined Architectures for 2-D Discrete Wavelet Transform and Its Inversion, " 2005 Asia Pacific Symposium on EMC (APEMC-2005), Taipei, Taiwan, Dec.6-9, 2005, pp.413-421. (EI)
[46]  Tze-Yun Sung, Yaw-Shih Shieh, Kuo-Jen Lin, "VLSI Implementation of a CORDIC-Based 2-D Discrete Cosine Transform and Its Inverse, " 2005 Asia Pacific Symposium on EMC (APEMC-2005), Taipei, Taiwan, Dec.6-9, 2005, pp.571-576. (EI)
[47]  Kuo-Jen Lin, Chih-Sung Shih, Tze-Yun Sung, Yaw-Shih Shieh, "A Free Jitter Phase Frequency Detector with Negligible Dead Zone, " 2005 Asia Pacific Symposium on EMC (APEMC-2005), Taipei, Taiwan, Dec.6-9, 2005, pp.397-400. (EI)
[48]  Kuo-Jen Lin, Chih-Sheng Yang, Tze-Yun Sung, Yaw-Shih Shieh, "A Full Band Low Power Low Phase Noise LC VCO with RF CMOS Varactor, " 2005 Asia Pacific Symposium on EMC (APEMC-2005), Taipei, Taiwan, Dec.6-9, 2005, pp.387-391. (EI)
[49]  Tze-Yun Sung, Chih-Sin Chen, "Hardware Implementation of High-Throughput 3-D Rotation for Graphic Engine Using Double Rotation CORDIC Algorithm, " 2005 National Computer Symposium (NCS-2005), Tainan, Taiwan, Dec. 15-16, 2005, MIE-2.
[50]  Tze-Yun Sung, Yaw-Shih Shieh, Kuo-Jen Lin, Cheui-Lu Chiu, "Design and Analysis of Pipelined Discrete Wavelet Transform Architectures, " 2005 National Computer Symposium (NCS-2005), Tainan, Taiwan, Dec. 15-16, 2005, OSB-1.
[51]  Tze-Yun Sung, Yaw-Shih Shieh, Mao-Jen Sun, "A High-Throughput and Memory-Efficiency 2-D DCT Architecture Based on CORDIC Rotation, " The 23rd Workshop on Combinatorial Mathematics and Computation Theory (Algo-2006), Da Yeh University, Changhua, Taiwan, April 28~29, 2006, pp.369-372.
[52]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, "An Efficient Line-Based Architecture for 2-D Lifting-Based DECT Using 9/7 Wavelet Filters, " The 23rd Workshop on Combinatorial Mathematics and Computation Theory (Algo-2006), Da Yeh University, Changhua, Taiwan, April 28~29, 2006, pp.305-308.
[53]  Tze-Yun Sung, Yaw-Shih Shieh, Huei-Ru Tsai, "VLSI Implementation of Double-Rotation CORDIC Arithmetic (DRCA), " 2006 Conference on Microelectronics Technology and Applications (2006-CMTA), National Kaohsiung Marine University, Kaohsiung, Taiwan, May 19, 2006, D-2.
[54]  Tze-Yun Sung, Yaw-Shih Shieh, Cheui-Lu Chiu, "High-Efficient Architectures for Forward and Inverse Discrete Wavelet Transform Using 4-tap Daubechies Filters, " 2006 Conference on Microelectronics Technology and Applications (2006-CMTA), National Kaohsiung Marine University, Kaohsiung, Taiwan, May 19, 2006, D-3.
[55]  Tze-Yun Sung, Yaw-Shih Shieh, Mao-Jen Sun, "VLSI Implementation of 2-D Discrete Cosine Transform Architecture Based on CORDIC Rotation, " 2006 Conference on Microelectronics Technology and Applications (2006-CMTA), National Kaohsiung Marine University, Kaohsiung, Taiwan, May 19, 2006, D-4.
[56]  Tze-Yun Sung, Yaw-Shih Shieh, Mao-Jen Sun, "A Parallel and Pipelined Architecture for 2-D CORDIC-Based Inverse Discrete Cosine Transform, " 2006 Conference on Microelectronics Technology and Applications (2006-CMTA), National Kaohsiung Marine University, Kaohsiung, Taiwan, May 19, 2006, D-5.
[57]  Tze-Yun Sung, Yaw-Shih Shieh, Kuo-Jen Lin, Sau-Jia Cheng, "A Low-Power and High-Efficiency Image Scalar Algorithm for LCD Display Controller, " 2006 Conference on Microelectronics Technology and Applications (2006-CMTA), National Kaohsiung Marine University, Kaohsiung, Taiwan, May 19, 2006, D-6.
[58]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, "High-Efficient Architectures for 2-D Lifting-Based Forward and Inverse Discrete Wavelet Transform Using 5/3 Wavelet Filter, " 2006 Conference on Microelectronics Technology and Applications (2006-CMTA), National Kaohsiung Marine University, Kaohsiung, Taiwan, May 19, 2006, D-8.
[59]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, "A High-Efficient Line-Based Architecture for 2-D Discrete Wavelet Transform Based on Lifting Scheme Using 9/7 Wavelet Filters, " 2006 Conference on Microelectronics Technology and Applications (2006-CMTA), National Kaohsiung Marine University, Kaohsiung, Taiwan, May 19, 2006, D-9.
[60]  Tze-Yun Sung, Yaw-Shih Shieh, Mao-Jen Sun, Chun-Wang Yu, "Cost-Effective Architectures for 2-D Forward and Inverse Discrete Cosine Transform Architecture, " 2006 Conference on Electronic Communication and Application (2006-CECA), Kaoshiung, Taiwan, July 06, 2006, BO-020.
[61]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, "High-Efficient Architectures for 2-D Lifting-Based Forward and Inverse Discrete Wavelet Transform, " 2006 Conference on Electronic Communication and Application (2006-CECA), Kaoshiung, Taiwan, July 06, 2006, BO-018.
[62]  Tze-Yun Sung, Yaw-Shih Shieh, Cheui-Lu Chiu, Chun-Wang Yu, "VLSI Architectures for 2-D Forward and Inverse Discrete Wavelet Transform Using 4-tap Daubechies Filters, " 2006 Conference on Electronic Communication and Application (2006-CECA), Kaoshiung, Taiwan, July 06, 2006, BO-019.
[63]  Tze-Yun Sung, Cheui-Lu Chiu, Yaw-Shih Shieh, Chun-Wang Yu, "Two Fast Architectures for 2-D DWT and IDWT Using 4-Tap Daubechies Filters, " 19th Computer Vision, Graphics, and Image Processing Conference (CVGIP-2006), Aug. 13-15, 2006, Taoyuan, Taiwan, pp.617-624.
[64]  Tze-Yun Sung, Yaw-Shih Shieh, Huei-Ru Tsai, Chun-Wang Yu, "A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic, " 19th Computer Vision, Graphics, and Image Processing Conference (CVGIP-2006), Aug. 13-15, 2006, Taoyuan, Taiwan, pp.1238-1242.
[65]  Tze-Yun Sung, Mao-Jen Sun, Hsi-Chin Hsin, Chun-Wang Yu, "Low-Power and High-Speed Architectures for 2-D DCT and IDCT Based on CORDIC Rotation, " 19th Computer Vision, Graphics, and Image Processing Conference (CVGIP-2006), Aug. 13-15, 2006, Taoyuan, Taiwan, pp.1024-1029.
[66]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, "Low-Power and Multiplierless Architectures for Line-Based 2-D DWT and IDWT, " 19th Computer Vision, Graphics, and Image Processing Conference (CVGIP-2006), Aug. 13-15, 2006, Taoyuan, Taiwan, pp.1232-1237.
[67]  Tze-Yun Sung, Yaw-Shih Shieh, Kuo-Jen Lin, Chao-Chia Cheng, "VLSI Implementation of A High-Efficient Image Scalar Algorithm for LCD Signal Processor, " 19th Computer Vision, Graphics, and Image Processing Conference (CVGIP-2006), Aug. 13-15, 2006, Taoyuan, Taiwan, pp.1032-1035.
[68]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, Hsi-Chin Hsin, "A High-Efficient Image Scalar Algorithm for LCD Signal Processor, " 4th Symposium on Photonic, Networking and Computing (PNC-2006) in conjunction with 9th Joint Conference on Information Sciences (JCIS-2006), Oct. 8-11, 2006, Kaohsiung, Taiwan, pp.1318-1321. (EI)
[69]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, Hsi-Chin Hsin, "A High-Efficient and Cost-Effective LCD Signal Processor, " 7th International Conference on Computer Vision, Pattern Recognition and Image Processing (CVPRIP-2006) in conjunction with 9th Joint Conference on Information Sciences (JCIS-2006), Oct. 8-11, 2006, Kaohsiung, Taiwan, pp.939-942. (EI)
[70]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, Hsi-Chin Hsin, "A High-Efficient Line-Based Architecture for 2-D Lifting-Based DWT Using 9/7 Wavelet Filters, " 9th International Conference on Computer Science and Informatics (CSI-2006) in conjunction with 9th Joint Conference on Information Sciences (JCIS-2006), Oct. 8-11, 2006, Kaohsiung, Taiwan, pp.626-629. (EI)
[71]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, Hsi-Chin Hsin, "An Efficient CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphics Rendering, " 9th International Conference on Computer Science and Informatics (CSI-2006) in conjunction with 9th Joint Conference on Information Sciences (JCIS-2006), Oct. 8-11, 2006, Kaohsiung, Taiwan, pp.739-742. (EI)
[72]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, Hsi-Chin Hsin, "High-Efficient Architectures for 2-D Lifting-Based Forward and Inverse Discrete Wavelet Transform, " 9th International Conference on Computer Science and Informatics (CSI-2006) in conjunction with 9th Joint Conference on Information Sciences (JCIS-2006), Oct. 8-11, 2006, Kaohsiung, Taiwan, pp.565-568. (EI)
[73]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, Hsi-Chin Hsin, "High-Speed and Low-Power Architectures for Forward and Inverse Discrete Wavelet Transform Using 4-Tap Baubechies Filters, " 9th International Conference on Computer Science and Informatics (CSI-2006) in conjunction with 9th Joint Conference on Information Sciences (JCIS-2006), Oct. 8-11, 2006, Kaohsiung, Taiwan, pp.518-521. (EI)
[74]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, Hsi-Chin Hsin, "VLSI Implementation of High-Efficient 2-D Lifting-Based DWT and IDWT Processors, " 2006 Workshop on Consumer Electronics and Signal Processing (WCEsp-2006), Chung Hua University, Hsinchu, Taiwan, Nov. 16, 2006, Session 5.
[75]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, Hsi-Chin Hsin, "Memory-Efficiency Multiplierless VLSI Architecture for 2-D DWT Using 9/7 Wavelet Filter, " 2006 Workshop on Consumer Electronics and Signal Processing (WCEsp-2006), Chung Hua University, Hsinchu, Taiwan, Nov. 16, 2006, Session 5.
[76]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, Hsi-Chin Hsin, "High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation, " The 7th International Conference on Parallel and Distributed Computing, Applications and Technologies(PDCAT-2006), 4-7 December 2006, Taipei, Taiwan, pp.191-196. (EI)
[77]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, Hsi-Chin Hsin, "A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering, " The 7th International Conference on Parallel and Distributed Computing, Applications and Technologies(PDCAT-2006), 4-7 December 2006, Taipei, Taiwan, pp.44-49. (EI)
[78]  Tze-Yun Sung, Chun-Wang Yu, Yaw-Shih Shieh, Hsi-Chin Hsin, "Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters, " The 7th International Conference on Parallel and Distributed Computing, Applications and Technologies(PDCAT-2006), 4-7 December 2006, Taipei, Taiwan, pp.185-190. (EI)
[79]  Tze-Yun Sung, Mao-Jen Sun, Yaw-Shih Shieh, Hsi-Chin Hsin, "Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation, " 2006 IEEE Pacific-Rim Symposium on Image and Video Technology (PSIVT-2006), Hsinchu, Taiwan, December 11-13, 2006, pp.802-811. (SCI)
[80]  Tze-Yun Sung, Hsi-Chin Hsin, "VLSI Implementation of CORDIC-Based Geometry Rotation for High-Speed 3-D Computer Graphic Systems, " 2006 International Workshop on Computer Architecture, VLSI, and Embedded Systems (In conjunction with International Computer Symposium(ICS-2006)), Taipei, Taiwan, Dec. 04-06, 2006, pp.123-128. (EI)
[81]  Tze-Yun Sung, Yaw-Shih Shieh and Hsi-Chin Hsin, "VLSI Implementation of Memory-Efficiency Multiplierless DCT and IDCT Processors, " 2006 International Workshop on Computer Architecture, VLSI, and Embedded Systems (In conjunction with International Computer Symposium(ICS-2006)), Taipei, Taiwan, Dec. 04-06, 2006, pp.117-122. (EI)
[82]  Hsi-Chin Hsin, Jenn-Jier Lien, Tze-Yun Sung, "A Hybrid SPIHT-EBC Image Coder, " The International MultiConference of Engineers and Computer Scientists 2007 (IMECS 2007), Hong Kong, China, March 21-23, 2007. (EI)
[83]  Tze-Yun Sung, "Memory-Efficient and High-Performance 2-D DCT and IDCT Processors Based on CORDIC Rotation, " The 7th WSEAS International Conference on MULTIMEDIA SYSTEMS and SIGNAL PROCESSING (MUSP'07), Hangzhou, China, April 15-17, 2007. (EI)
[84]  Tze-Yun Sung, "Memory-Efficient and High-Performance Parallel-Pipelined Architectures for 5/3 Forward and Inverse Discrete Wavelet Transform, " The 7th WSEAS International Conference on MULTIMEDIA SYSTEMS and SIGNAL PROCESSING (MUSP'07), Hangzhou, China, April 15-17, 2007. (EI)
[85]  Tze-Yun Sung, "Low-Power and High-Performance 2-D DWT and IDWT Architectures Based on 4-tap Daubechies Filters, " The 7th WSEAS International Conference on MULTIMEDIA SYSTEMS and SIGNAL PROCESSING (MUSP'07), Hangzhou, China, April 15-17, 2007. (EI)
[86]  Tze-Yun Sung, "Numerical Accuracy and Hardware Trade-Offs for Fixed-Point CORDIC Processor for Digital Signal Processing System, " The 7th WSEAS International Conference on MULTIMEDIA SYSTEMS and SIGNAL PROCESSING (MUSP'07), Hangzhou, China, April 15-17, 2007. (EI)
[87]  Tze-Yun Sung, "Memory-Efficient and High-Speed Line-Based Architecture for 2-D Discrete Wavelet Transform with Lifting Scheme, " The 7th WSEAS International Conference on MULTIMEDIA SYSTEMS and SIGNAL PROCESSING (MUSP'07), Hangzhou, China, April 15-17, 2007. (EI)
[88]  Tze-Yun Sung, "VLSI Implementation of High-Performance CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphic Systems, " The 7th WSEAS International Conference on INSTRUMENTATION, MEASUREMENT, CIRCUITS and SYSTEMS (IMCA '07), Hangzhou, China, April 15-17, 2007. (EI)
[89]  Hsi-Chin Hsin, Tze-Yun Sung, "An Efficient Rearrangement of Wavelet Packet Coefficients for Embedded Quad-Tree Image Coding, " The 7th WSEAS International Conference on MULTIMEDIA SYSTEMS and SIGNAL PROCESSING (MUSP'07), Hangzhou, China, April 15-17, 2007. (EI)