Advances in Computing

Advances in Computing deals with the theoretical foundations of information and computation and their implementation and application in computer systems. It publishes regular papers and special issues on specific topics of interest to international audiences of educational researchers.


Sotirios Ziavras

Editorial Board Member of Advances in Computing

Professor, New Jersey Institute Of Technology, USA

Research Areas

Computer Architecture, Embedded Systems, Parallel Computing, Reconfigurable Computing

Education

1990D.Sc.Computer Science from George Washington University
1985M.Sc.Electrical and Computer Engineering from Ohio University
1984DiplomaElectrical Engineering from the National Technical University of Athens (NTUA), Greece

Experience

2001-presentProfessor of Electrical and Computer Engineering & Director of the Computer Architecture and Parallel Processing Laboratory, New Jersey Institute of Technology
2005Distinguished Professor, Chung-Ang University, Seoul, Korea
1998-1999Research Associate, University of Maryland, College Park
1995-2001Associate Professor of Electrical and Computer Engineering & Computer and Information Science, New Jersey Institute of Technology
1990-1995Assistant Professor of Electrical and Computer Engineering, New Jersey Institute of Technology
1990Visiting Professor, George Mason University
1985-1989Distinguished Graduate Teaching Assistant and Research Assistant, George Washington University

Academic Achievement

Marquis Who's Who in Science and Engineering
Marquis Who's Who in America
Marquis Who's Who in the World
Marquis Who's Who in the East
Marquis Who's Who in American Education
Who's Who in Engineering Education
Received a Research Initiation Award from the National Science Foundation in 1991
Received in 1996 an NSF/DARPA (also sponsored by NASA) New Millennium Computing Point Design Studies grant for the design and feasibility analysis of a parallel computer that could achieve by the year 2005 near PetaFLOPS performance

Membership

Member of the IEEE (Senior member), Pattern Recognition Society, Greek Chamber of Engineers, and Eta Kappa Nu

Publications: Conferences/Workshops/Symposiums/Journals/Books

[1]  S. Wang, J. Hu and S.G. Ziavras, "Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays," IEEE Transactions on Very Large Scale Integration Systems. Accepted for publication.
[2]  I. Sajid, M.M. Ahmed and S.G. Ziavras, "Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm," Journal of Signal Processing Systems, accepted for publication.
[3]  S. Wang, J. Hu and S.G. Ziavras, "Exploring BTB Access Filtering for Low-Energy and High-Performance Microarchitectures," IET Computers & Digital Techniques, Accepted for publication.
[4]  N.B. Guinde and S.G. Ziavras, "Efficient Hardware Support for Pattern Matching in Network Intrusion Detection," Computers and Security (The official journal of Technical Committee 11 (computer security) of the International Federation of Information Processing), Volume 29, No. 7, October 2010, pp. 756-769.
[5]  S. Motahari, S.G. Ziavras and Q. Jones, "Online Anonymity Protection in Computer-Mediated Communications," IEEE Transactions on Information Forensics & Security, Vol. 5, No. 3, September 2010, pp. 570-580.
[6]  S.F. Beldianu, R. Rojas-Cessa, E. Oki and S.G. Ziavras, "Scheduling for Input-Queued Packet Switches by a Re-configurable Parallel Match Evaluator," IEEE Communications Letters, Vol. 14, No. 4, April 2010, pp. 357-359.
[7]  M.Z. Hasan and S.G. Ziavras, "Customized Kernel Execution on Reconfigurable Hardware for Embedded Applications," Embedded Hardware Design, Microprocessors and Microsystems, Vol. 33, No. 3, May 2009, pp. 211-220.
[8]  S. Wang, J. Hu and S.G. Ziavras, "On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors," IEEE Transactions on Computers, Vol. 58, No. 9, September 2009, pp. 1171-1184.
[9]  J. Hu, S. Wang and S.G. Ziavras, "On the Exploitation of Narrow-Width Values for Improving Register File Reliability," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 17, No. 7, July 2009, pp. 953-963.
[10]  X. Tang, C.N. Manikopoulos and S.G. Ziavras, "Generalized Anomaly Detection Model for Windows-Based Malicious Program Behavior," International Journal of Network Security, Vol. 7, No. 3, Nov. 2008, pp. 428-435.
[11]  S. Wang, J. Hu and S.G. Ziavras, "Self-Adaptive Data Caches for Soft-Error Reliability," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 8, August 2008, pp. 1503-1507.
[12]  D. Jin and S.G. Ziavras, "Robust Scalability Analysis and SPM Case Studies," The Journal of Supercomputing, Vol. 43, No. 3, March 2008, pp. 199-223.
[13]  S. Wang, H. Yang, J. Hu and S.G. Ziavras, "Asymmetrically Banked Value-Aware Register Files for Low Energy and High Performance," Microprocessors and Microsystems, Vol. 32, No. 3, May 2008, pp. 171-182.
[14]  M.Z. Hasan and S.G. Ziavras, "Partially Reconfigurable Vector Processors for Embedded Systems," Journal of Computers, Vol. 2, No. 9, Nov. 2007, pp. 60-66.
[15]  H. Yang, S.G. Ziavras and J. Hu, "FPGA-based Vector Processing for Matrix Operations," International Journal of High Performance Systems Architecture, Vol. 1, No. 2, 2007, pp. 89-97 (invited).
[16]  X. Wang, S.G. Ziavras, C. Nwankpa, J. Johnson and P. Nagvajara, "Parallel Solution of Newton's Power Flow Equations on Configurable Chips," International Journal of Electrical Power and Energy Systems, Vol. 29, No. 5 , June 2007, pp. 422-431.
[17]  S.G. Ziavras, A. Gerbessiotis, and R. Bafna, "A Co-Processor Design to Support MPI Primitives in Configurable Multiprocessors," Integration, the VLSI Journal, Vol. 40, No. 3, April 2007, pp. 235-252 ("one of the most downloadable articles" from the journal's web site in 2006, according to Elsevier Science)..
[18]  X. Xu and S.G. Ziavras, "A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers," IEICE Transactions on Information and Systems, Special Issue on Parallel/Distributed Computing and Networking, Vol. E89-D, No. 2, February 2006, pp. 639-646.
[19]  X. Wang and S.G. Ziavras, "Exploiting Mixed-Mode Parallelism for Matrix Operations on the HERA Heterogeneous Reconfigurable Architecture through Reconfiguration," IEE Proceedings, Computers and Digital Techniques, Vol. 153, No. 4, July 2006, pp. 249-260.
[20]  D. Jin and S.G. Ziavras, "Modeling Distributed Data Representation and its Effect on Parallel Data Accesses," Journal of Parallel and Distributed Computing, Special Issue on Design and Performance of Networks for Super-, Cluster-, and Grid-Computing, Vol. 65, No. 10, October 2005, pp. 1281-1289.
[21]  S.G. Haridas and S.G. Ziavras, "FPGA Implementation of a Cholesky Algorithm for a Shared-Memory Multiprocessor Architecture," Parallel Algorithms and Applications, Vol. 19, No. 4, Dec. 2004, pp. 211-226. (The name of the journal was changed in 2005 to International Journal of Parallel, Emergent and Distributed Systems.)
[22]  D. Jin and S.G. Ziavras, "A Super-Programming Approach for Mining Association Rules in Parallel on PC Clusters," IEEE Transactions on Parallel and Distributed Systems, Vol. 15, No. 9, Sept. 2004, pp. 783-794.
[23]  D. Jin and S.G. Ziavras, "A Super-Programming Technique for Large Sparse Matrix Multiplication on PC Clusters," IEICE (The Institute of Electronics, Information and Communication Engineers) Transactions on Information and Systems, Special Issue on Hardware/Software Support for High Performance Scientific and Engineering Computing, Vol. E87-D, No. 7, July 2004, pp. 1774-1781.
[24]  X. Wang and S.G. Ziavras, "Parallel LU Factorization of Sparse Matrices on FPGA-Based Configurable Computing Engines," Concurrency and Computation: Practice and Experience, Vol. 16, No. 4, April 2004, pp. 319-343.
[25]  M.Z. Hasan and S.G. Ziavras, "An FPGA-Based Vector Computer for Sparse Matrix-Vector Processing," WSEAS Transactions on Computers, Vol. 3, No. 2, April 2004, pp. 453-460.
[26]  X. Xu and S.G. Ziavras, "A Configurable and Scalable SIMD Machine for Computation-Intensive Applications," WSEAS Transactions on Computers, Vol. 2, No. 4, Oct. 2003, pp. 1021-1029 (invited paper).
[27]  S.G. Ziavras, "Processor Design Employing Dataflow Concurrency," Microprocessors and Microsystems, Vol. 27, No. 4, May 2003, pp. 199-220 ("one of the most downloadable articles" of the journal between Jan. and May 2003, according to Elsevier Science).
[28]  S.G. Ziavras, Q. Wang and P. Papathanasiou, "Viable Architectures for High-Performance Computing," The Computer Journal, Vol. 46, No. 1, Jan. 2003, pp. 36-54.
[29]  S. Ingersoll and S.G. Ziavras, "Intelligent Memories for Dataflow Computation and Emulation on Field-Programmable Gate Arrays," Microprocessors and Microsystems, Vol. 26, No. 6, Aug. 2002, pp. 263-280.
[30]  T.I. Golota and S.G. Ziavras, "A Universal, Dynamically Adaptable and Programmable Network Router for Parallel Computers," VLSI Design, Vol. 12, No. 1, Febr. 2001, pp. 25-52.
[31]  S.G. Ziavras, H. Grebel, A.T. Chronopoulos and F. Marcelli, "A New-Generation Parallel Computer and its Performance Evaluation," Future Generation Computer Systems, Vol. 17, No. 3, Dec. 2000, pp. 315-333.
[32]  S.G. Ziavras and S. Krishnamurthy, "Evaluating the Communications Capabilities of the Generalized Hypercube Interconnection Network," Concurrency: Practice and Experience, Vol. 11, No. 6, May 1999, pp. 281-300.
[33]  S.G. Ziavras, "Investigation of Various Mesh Architectures with Broadcast Buses for High Performance Computing," VLSI Design, Special Issue on High Performance Bus-Based Architectures, R. Lin and S. Olariu (Eds.), Vol. 9, No. 1, Jan. 1999, pp. 29-54.
[34]  X. Li, S.G. Ziavras and C.N. Manikopoulos, "Parallel Generation of Adaptive Multiresolution Structures for Image Processing," Concurrency: Practice and Experience, Vol. 9, No. 4, April 1997, pp. 241-254.
[35]  M. Kahn and S.G. Ziavras, "Material Identification Algorithms for Parallel Systems," Computers and Electrical Engineering, Vol. 22, No. 5, Sept. 1996, pp. 325-342.
[36]  S.G. Ziavras and A. Mukherjee, "Data Broadcasting and Reduction, Prefix Computation, and Sorting on Reduced Hypercube Parallel Computers," Parallel Computing, Vol. 22, June 1996, pp. 595-606.
[37]  X. Li, S.G. Ziavras and C.N. Manikopoulos, "Parallel DSP Algorithms on TurboNet: An Experimental Hybrid Message-Passing/Shared-Memory Architecture," Concurrency: Practice and Experience, Vol. 8, No. 5, June 1996, pp. 387-411.
[38]  S.G. Ziavras and M.A. Sideras, "Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers," International Journal of Pattern Recognition and Artificial Intelligence, Special Issue on Parallel Image Analysis: Theory and Applications, L.S. Davis, K. Inoue, M. Nivat, A. Rosenfeld, and P.S.P. Wang (Eds.), Vol. 9, No. 4, Aug. 1995, pp. 679-698.
[39]  S.G. Ziavras, "Scalable Multifolded Hypercubes for Versatile Parallel Computers," Parallel Processing Letters, Vol. 5, No. 2, June 1995, pp. 241-250.
[40]  S.G. Ziavras and P. Meer, "Adaptive Multiresolution Structures for Image Processing on Parallel Computers," Journal of Parallel and Distributed Computing, Vol. 23, No. 3, Dec. 1994, pp. 475-483.
[41]  S.G. Ziavras, "RH: A Versatile Family of Reduced Hypercube Interconnection Networks," IEEE Transactions on Parallel and Distributed Systems, Vol. 5, No. 11, Nov. 1994, pp. 1210-1220.
[42]  S.G. Ziavras and N.G. Haravu, "Processor Allocation Strategies for Modified Hypercubes," IEE Proceedings E: Computers and Digital Techniques, May 1994, Vol. 141, No. 3, pp. 196-204.
[43]  S.G. Ziavras and D.P. Shah, "High-Performance Emulation of Hierarchical Structures on Hypercube Supercomputers," Concurrency: Practice and Experience, Vol. 6, No. 2, April 1994, pp. 85-100.
[44]  S.G. Ziavras and M. Khatri, "Binary Trees of Modified Hypercubes: A Family of Networks for Hypercube-Like Parallel Computers," International Journal of Electronics, Vol. 76, No. 1, Jan. 1994, pp. 27-36.
[45]  S.G. Ziavras, "Connected Component Labelling on the BLITZEN Massively Parallel Processor," Image and Vision Computing, Vol. 11, No. 10, Dec. 1993, pp. 665-668.
[46]  S.G. Ziavras, "Efficient Mapping Algorithms for a Class of Hierarchical Systems," IEEE Transactions on Parallel and Distributed Systems, Vol. 4, No. 11, Nov. 1993, pp. 1230-1245.
[47]  S.G. Ziavras and M.A. Siddiqui, "Pyramid Mappings onto Hypercubes for Computer Vision: Connection Machine Comparative Study," Concurrency: Practice and Experience, Vol. 5, No. 6, Sept. 1993, pp. 471-489.
[48]  S.G. Ziavras, "Mapping Single and Multiple Multilevel Structures onto the Hypercube," IEE Proceedings E: Computers and Digital Techniques, Vol. 140, No. 2, March 1993, pp. 115-118.
[49]  S.G. Ziavras, "On the Problem of Expanding Hypercube-Based Systems," Journal of Parallel and Distributed Computing, Vol. 16, No. 1, Sept. 1992, pp. 41-53.
[50]  S.G. Ziavras and N.A. Alexandridis, "Improved Algorithms for Translation of Pictures Represented by Leaf Codes," Image and Vision Computing, Vol. 6, No. 1, Febr. 1988, pp. 13-20.
[51]  S.G. Ziavras, "History of Computation," The Encyclopedia of Life Support Systems, Developed under the Auspices of the UNESCO (United Nations Educational, Scientific and Cultural Organization), Eolss Publishers, Oxford, United Kingdom, Theme 6.45: Computer Science and Engineering, 2002 (nominated). Also available at http://www.eolss.net, 2004. (The average number of daily visitors per week to this web site was approximately 81,000 in 2006. The one-day high was over 99,000 visitors. According to UNESCO/EOLSS, these numbers continuously increase.)
[52]  S.G. Ziavras, "Computer Systems," The Encyclopedia of Life Support Systems, Developed under the Auspices of the UNESCO, Eolss Publishers, Oxford, United Kingdom, Theme 6.45: Computer Science and Engineering, 2002 (nominated). Also available at http://www.eolss.net, 2004.
[53]  S. Ingersoll and S.G. Ziavras, "Dataflow Computation on Reconfigurable Gate Arrays," Advances in Signal Processing and Computer Technologies, G. Antoniou, N. Mastorakis, and O. Panfilov (Eds.), World Scientific and Engineering Society Press, 2001, pp. 367-372.
[54]  S. G. Ziavras and C.N. Manikopoulos, "Matrix Multiplication on an Experimental Parallel System with Hybrid Architecture," Signal Processing, Communications and Computer Science, N. Mastorakis (Ed.), World Scientific and Engineering Society Press, 2000, pp. 7-12.
[55]  S.G. Ziavras and Q. Wang, "Robust Interprocessor Connections for Very-High Performance," Robust Communication Networks: Interconnection and Survivability, N. Dean, F. Hsu, and R. Ravi (Eds.), American Mathematical Society, 2000, pp. 143-167.
[56]  S.G. Ziavras and M.A. Sideras, "Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers," Parallel Image Analysis: Theory and Applications, L.S. Davis, K. Inoue, M. Nivat, A. Rosenfeld, and P.S.P. Wang (Eds.), World Scientific, 1996, pp. 23-42.
[57]  S.G. Ziavras, "Generalized Reduced Hypercube Interconnection Networks for Massively Parallel Computers," Networks for Parallel Computations, D.F. Hsu, A. Rosenberg, and D. Sotteau (Eds.), American Mathematical Society, 1995, pp. 307-325.
[58]  S.G. Ziavras, "Connection Machine Results for Pyramid Embedding Algorithms," Lecture Notes in Computer Science, L. Bouge, M. Cosnard, Y. Robert, D. Trystram (Eds.), Vol. 634, Springer-Verlag, 1992, pp. 31-36.
[59]  S.G. Ziavras and L.S. Davis, "Fast Addition on the Fat Pyramid and its Simulation on the Connection Machine," From Pixels to Features, J.C. Simon (Ed.), Elsevier Science, 1989, pp. 373-382.
[60]  N.A. Alexandridis, N.A. Bilalis and S. Ziavras, "Improved Object Boundary Representation by Investigating Neighbor Quadrants in a Quadtree Structure of an Image," Digital Techniques in Simulation, Communication and Control, S.G. Tzafestas (Ed.), Elsevier Science, 1985, pp. 195-201.
[61]  X. Tang, C. Manikopoulos and S.G. Ziavras, "State Transition Analysis to Detect Malicious Program Behavior," 12th WSEAS International Conference on Computers, Heraklion, Crete, Greece, July 22-25, 2008, pp. 560-565.
[62]  X. Xu and S.G. Ziavras, "A Configurable and Scalable SIMD Machine for Computation-Intensive Applications," 3rd WSEAS International Conference on Systems Theory and Scientific Computation, Rhodes, Greece, Nov.15-17, 2003.
[63]  S.G. Ziavras, H. Grebel and A. Chronopoulos, "A Low-Complexity Parallel System for Gracious, Scalable Performance. Case Study for Near PetaFLOPS Computing," 6th Symposium on the Frontiers of Massively Parallel Computation, Special Session on the NSF/DARPA/NASA-funded New Millennium Computing Point Designs, Annapolis, Maryland, Oct. 27-31, 1996, pp. 363-370.
[64]  S.G. Ziavras, H. Grebel and A.T. Chronopoulos, "A Scalable/Feasible Parallel Computer Implementing Electronic and Optical Interconnections for 156 TeraOPS Minimum Performance," PetaFlops Architecture Workshop organized for the NSF/DARPA/NASA-funded Point Designs, Oxnard, California, April 22-25, 1996, pp. 235-266.
[65]  L.S. Davis, D. DeMenthon, T. Bestul, D. Harwood, H.V. Srinivasan and S. Ziavras, "RAMBO-Vision and Planning on the Connection Machine," 6th Scandinavian Conference on Image Analysis, Oulu, Finland, June 19-22, 1989, pp. 1-14.
[66]  L.S. Davis, D. DeMenthon, T. Bestul, D. Harwood, H.V. Srinivasan and S. Ziavras, "RAMBO-Vision and Planning on the Connection Machine," DARPA Image Understanding Workshop, Palo Alto, California, May 23-26, 1989, pp. 631-639.
[67]  S.F. Beldianu and S.G. Ziavras, "On-Chip Vector Coprocessor Sharing for Multicores," The 19th Euromicro International Conference on Parallel, Distributed and Network-Based Computing, Ayia Napa, Cyprus, February 9-11, 2011, pp. 431-438 (IEEE Computer Society).
[68]  N.B. Guinde, S.G. Ziavras and R. Rojas-Cessa, "Efficient Packet Classification on FPGAs also Targeting at Manageable Memory Consumption," 4th International Conference on Signal Processing and Communication Systems, Gold Coast, Australia, December 13-15, 2010, accepted for publication (9/19/2010).
[69]  I. Sajid, S.G. Ziavras and M.M Ahmed, "Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance," 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, Lille, France, September 1-3, 2010, pp. 763-770.
[70]  S. Wang, J. Hu and S.G. Ziavras, "TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array," IEEE Computer Annual Symposium on VLSI, Lixouri, Kefalonia, Greece, July 5-7, 2010, pp. 310-315.
[71]  I. Sajid and S.G. Ziavras, "FPGA-based Normalization for Modified Gram-Schmidt Orthogonalization," International Conference on Computer Vision Theory and Applications, Angers, France, May 17-21, 2010, pp. 227-232 (acceptance rate: 13%).
[72]  N.B. Guinde and S.G. Ziavras, "Novel FPGA-Based Signature Matching for Deep Packet Inspection," 4th IFIP WG 11.2 International Workshop on Information Security Theory and Practices: Security and Privacy of Pervasive Systems and Smart Devices, Passau, Germany, April 12-14, 2010 (acceptance rate: 30%) Lecture Notes in Computer Science, Springer Subseries on Security and Cryptology, Vol. 6033, pp. 261-276.
[73]  N.B. Guinde, X. Tang, R. Sutaria, S.G. Ziavras and C.N. Manikopoulos, "FPGA-based Static Analysis Tool for Detecting Malicious Binaries," 2nd International Conference on Computer and Automation Engineering, Singapore, February 26-28, 2010, Volume 2, pp. 639-643.
[74]  I. Sajid, M.M. Ahmed and S.G. Ziavras, "Pipelined Implementation of Fixed point Square Root in FPGA Using Modified Non-Restoring Algorithm," 2nd International Conference on Computer and Automation Engineering, Singapore, February 26-28, 2010, Volume 3, pp. 226-230.
[75]  S. Motahari, S. Ziavras and Q. Jones, "Preventing Unwanted Social Inferences with Classification Tree Analysis," 21st IEEE International Conference on Tools with Artificial Intelligence, Newark, New Jersey, November 2-5, 2009, pp. 500-507 (acceptance rate: 26.58%).
[76]  S. Motahari, S. Ziavras, M. Naaman, M. Ismail and Q. Jones, "Social Inference Risk Modeling in Mobile and Social Applications," IEEE International Conference on Information Privacy, Security, Risk and Trust (PASSAT2009), Vancouver, Canada, August 29-31, 2009. In the Proceedings of 12th the IEEE International Conference on Computational Science and Engineering, Vol. 3, pp. 125-132 (13% acceptance rate).
[77]  S. Beldianu, R. Rojas-Cessa, E. Oki and S.G. Ziavras, "Re-configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches," 18th IEEE International Conference on Computer Communications and Networks, San Francisco, California, August 2-6, 2009.
[78]  B.-Il Kim and S.G. Ziavras, "Low-Power Multiplierless DCT for Image/Video Coders," 13th IEEE International Symposium on Consumer Electronics, Mielparque-Kyoto, Kyoto, Japan, May 25-28, 2009, pp. 133-136.
[79]  S. Wang, J. Hu, S.G. Ziavras and S.W. Chung, "Exploiting Narrow-Width Values for Thermal-Aware Register File Designs," Design, Automation and Test in Europe (DATE), Nice, France, April 20-24, 2009.
[80]  S. Motahari, S. Ziavras, R.P. Schuler and Q. Jones, "Identity Inference as a Privacy Risk in Computer-Mediated Communication," 42nd Hawaii International Conference on System Sciences (HICSS 2009), Waikoloa, Hawaii, January 5-8, 2009.
[81]  N.A. Al-Saber, S. Oberoi, R. Rojas-Cessa and S.G. Ziavras, "Concatenating Packets in Variable-Length Input-Queued Packet Switches with Cell-Based and Packet-Based Scheduling," IEEE Sarnoff Symposium, Princeton, New Jersey, April 28-30, 2008.
[82]  S. Wang, J. Hu and S.G. Ziavras, "BTB Access Filtering: A Low Energy and High Performance Design," IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, April 7-9, 2008, pp. 81-86 (chosen by the reviewers and the Program Committee as one of six papers candidate for the Best Paper Award out of 220 submitted papers: 2.72%)
[83]  M.Z. Hasan and S.G. Ziavras, "Reconfiguration Framework for Multi-kernel Embedded Applications," 2nd Annual Reconfigurable and Adaptive Architectures Workshop (in conjunction with the 40th Annual IEEE/ACM International Symposium on Microarchitecture), Chicago, Illinois, December 1, 2007.
[84]  M.Z. Hasan and S.G. Ziavras, "Resource Management for Dynamically-Challenged Reconfigurable Systems," 12th IEEE Conference on Emerging Technologies and Factory Automation, Patras, Greece, Sept. 25-28, 2007, pp. 119-126.
[85]  X. Wang, S.G. Ziavras and J. Hu, "Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors," International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, June 25-28, 2007.
[86]  S. Wang, H. Yang, J. Hu, and S.G. Ziavras, "Asymmetrically Banked Value-Aware Register Files," IEEE Computer Society Annual Symposium on VLSI, Porto Alegre, Brazil, May 9-11, 2007, pp. 363-368.
[87]  H. Yang, S. Wang, S.G. Ziavras and J. Hu, "Vector Processing Support for FPGA-Oriented High Performance Applications," IEEE Computer Society Annual Symposium on VLSI, Porto Alegre, Brazil, May 9-11, 2007, pp. 447-448.
[88]  D. Jin and S.G. Ziavras, "A Study of Some Data Exchange Protocols for Grid Computing," 3rd International Conference on Networking and Services, Athens, Greece, June 19-25, 2007.
[89]  K. Bhargava, S.G. Ziavras and R. Rojas-Cessa, "Measuring Network Parameters with Hardware Support,"3rd IEEE International Conference on Networking and Services, Athens, Greece, June 19-25, 2007.
[90]  H. Yang, S.G. Ziavras and J. Hu, "FPGA-based Vector Processing for Matrix Operations," IEEE International Conference on Information Technology: New Generations, Las Vegas, Nevada, April 2-4, 2007, pp. 989-994.
[91]  M.Z. Hasan and S.G. Ziavras, "Runtime Partial Reconfiguration for Embedded Vector Processors," IEEE International Conference on Information Technology: New Generations, Las Vegas, Nevada, April 2-4, 2007, pp. 983-988.
[92]  X. Wang and S.G. Ziavras, "Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors," 8th IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, California, March 26-28, 2007, pp. 386-391.
[93]  X. Wang, S.G. Ziavras and J. Hu, "System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors," 24th International Conference on Computer Design, San Jose, California, October 1-4, 2006, pp. 411-416 (acceptance rate: 30%).
[94]  S. Wang, J. Hu and S.G. Ziavras, "On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors," 6th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Samos, Greece, July 17-20, 2006, pp. 14-20 (40% of the 130 submitted papers were accepted).
[95]  J. Hu, S. Wang and S.G. Ziavras, "In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability," International Conference on Dependable Systems and Networks, Philadelphia, Pennsylvania, June 25-28, 2006, pp. 281-290 (18% of the 187 submitted papers were accepted).
[96]  X. Wang and S.G. Ziavras, "A Framework for Dynamic Resource Management and Scheduling on Reconfigurable Mixed-Mode Multiprocessors," IEEE International Conference on Field-Programmable Technology, Singapore, Dec. 11-14, 2005, pp. 51-58 (22% of the 143 submitted papers were accepted).
[97]  X. Xu, S.G. Ziavras, and T.-G. Chang, "An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method," IFIP International Conference on Embedded and Ubiquitous Computing, Nagasaki, Japan, Dec. 6-9, 2005, pp. 458-468 (30% of the 375 submitted papers were accepted). Lecture Notes in Computer Science, Springer-Verlag, Vol. 3824.
[98]  R. Rojas-Cessa, Z. Dong and S.G. Ziavras, "Load-Balanced CICB Packet Switch with Support for Long Round-Trip Times," IEEE Global Telecommunications Conference, St. Louis, Missouri, Nov. 28-Dec.2, 2005, pp. 1002-1006.
[99]  X. Wang and S.G. Ziavras, "Adaptive Scheduling of Array-Intensive Applications on Mixed-Mode Reconfigurable Multiprocessors," 39th IEEE Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, Oct. 30—Nov. 2, 2005, pp. 1642-1646.
[100]  M.Z. Hasan, S.G. Ziavras and T.-G. Chang, "Power Flow Analysis on an FPGA-Based Vector Computer," IASTED Conference on Power and Energy Systems, Marina del Ray, California, October 24-26, 2005, pp. 96-99.
[101]  J.S. Hu, G.M. Link, J.K. John, S. Wang, and S.G. Ziavras, "Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures," 10th Asia-Pacific Computer Systems Architecture Conference, Singapore, Oct. 24-26, 2005, pp. 200-214.
[102]  X. Xu and S.G. Ziavras, "H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication," IEEE International Conference on Computer Design, San Jose, California, Oct. 2-5, 2005, pp. 671-676 (32% of the 313 submitted papers were accepted).
[103]  J.K. John, J.S. Hu and S.G. Ziavras, "Optimizing the Thermal Behavior of Subarrayed Data Caches," IEEE International Conference on Computer Design, San Jose, California, Oct. 2-5, 2005, pp. 625-630 (32% of the 313 submitted papers were accepted).
[104]  X. Xu and S.G. Ziavras, "A Hierarchically-Controlled SIMD Machine for 2D DCT on FPGAs," IEEE International Systems-On-Chip Conference, Herndon, Virginia, Sept. 25-28, 2005, pp. 276-279 (33% of the 175 submitted papers were accepted as regular papers).
[105]  M.Z. Hasan and S.G. Ziavras, "FPGA-Based Vector Processing for Solving Sparse Sets of Equations," IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, April 17-20, 2005, pp. 331-332.
[106]  X. Wang and S.G. Ziavras, "Mixed-Mode Scheduling for Parallel LU Factorization of Sparse Matrices on the Reconfigurable HERA Computer," Advances in Computer Science and Technology, St. Thomas, U.S. Virgin Islands, Nov. 22-24, 2004, pp. 105-100.
[107]  X. Wang and S.G. Ziavras, "HERA: A Reconfigurable and Mixed-Mode Parallel Computing Engine on Platform FPGAs," 16th International Conference on Parallel and Distributed Computing and Systems, MIT, Cambridge, Massachusetts, Nov. 9-11, 2004, pp. 374-379.
[108]  X. Wang and S.G. Ziavras, "A Configurable Multiprocessor and Dynamic Load Balancing for Parallel LU Factorization," 5th International Workshop on Parallel and Distributed Scientific and Engineering Computing (in conjunction with the 18th IEEE International Parallel and Distributed Processing Symposium), Santa Fe, New Mexico, April 26-30, 2004 (student received an NJIT Student Achievement Award to present the paper).
[109]  X. Wang and S.G. Ziavras, "Performance Optimization of an FPGA-Based Configurable Multiprocessor for Matrix Operations," IEEE International Conference on Field-Programmable Technology, The University of Tokyo, Japan, Dec. 15-17, 2003, pp. 303-306.
[110]  M.Z. Hasan and S.G. Ziavras, "An FPGA-Based Vector Computer for Sparse Matrix-Vector Processing," WSEAS Conference on Mathematical Methods and Computational Techniques in Electrical Engineering, Athens, Greece, Dec. 29-31, 2003.
[111]  D. Jin and S.G. Ziavras, "A Super-Programming Technique for Large Sparse Matrix Multiplication on PC Clusters," 2nd Workshop on Hardware/Software Support for High Performance Scientific and Engineering Computing (in conjunction with the 12th International Conference on Parallel Architectures and Compilation Techniques-PACT03), New Orleans, Louisiana, Sept. 27—Oct. 1, 2003, pp. 63-70.
[112]  X. Xu and S.G. Ziavras, "A Configurable and Scalable SIMD Machine for Computation-Intensive Applications," 3rd WSEAS Conference on Applied Informatics and Communications, Rhodes, Greece, Nov. 15-17, 2003.
[113]  D. Jin and S.G. Ziavras, "Load Balancing on PC Clusters With the Super-Programming Model," Workshop on Compile/Runtime Techniques for Parallel Computing (in conjunction with the International Conference on Parallel Processing-ICPP03), Kaohsiung, Taiwan, Oct. 6-9, 2003.
[114]  X. Wang and S.G. Ziavras, ``Parallel Direct Solution of Linear Equations on FPGA-Based Machines," Workshop on Parallel and Distributed Real-Time Systems (in conjunction with the 17th Annual IEEE International Parallel and Distributed Processing Symposium), Nice, France, April 22-23, 2003.
[115]  X. Xu and S.G. Ziavras, "Iterative Methods for Solving Linear Systems of Equations on FPGA-Based Machines," ISCA 18th International Conference on Computers and their Applications, Honolulu, Hawaii, March 26-28, 2003, pp. 472-475.
[116]  X. Wang, S.G. Ziavras and J. Savir, "Efficient LU Factorization on FPGA-Based Machines," Seventh IASTED International Multi-Conference on Power and Energy Systems, Palm Springs, California, Febr. 24-26, 2003, pp. 459-464.
[117]  C.N. Manikopoulos, S.G. Ziavras and B. Christou, "A Low-Cost High-Performance Shared-Memory Multiprocessor System for Real-Time Applications," International Conference on Computing and Information Technologies, Montclair, New Jersey, Oct. 2001, pp. 127-136.
[118]  S. Ingersoll and S.G. Ziavras, "Dataflow Computation on Reconfigurable Gate Arrays," Fifth World Conference on Computers, Rethymno, Crete, Greece, July 8-15, 2001, pp. 7031-7036.
[119]  S.G. Ziavras, "Versatile Processor Design for Efficiency and High Performance," International Symposium on Parallel Architectures, Algorithms, and Networks, Dallas, Texas, Dec. 7-9, 2000, pp. 266-271.
[120]  S. G. Ziavras and C.N. Manikopoulos, "Matrix Multiplication on an Experimental Parallel System with Hybrid Architecture," Fourth World Conference on Computers, Athens, Greece, July 2000, pp. 3581-3586.
[121]  T. Golota and S.G. Ziavras, "A Versatile Router for High-Performance Computing," International Conference on Parallel and Distributed Computing and Systems, MIT, Cambridge, Massachusetts, Nov. 3-6, 1999, pp. 738-743.
[122]  S.G. Ziavras, Q. Wang, N. Alexandridis and P. Papathanasiou, "Cost and Performance Analysis of Scalable Parallel Architectures," International Conference on Parallel and Distributed Computing and Systems, MIT, Cambridge, Massachusetts, Nov. 3-6, 1999, pp. 113-118.
[123]  Q. Wang and S.G. Ziavras, "Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities," International Symposium on Parallel Architectures, Algorithms, and Networks, Freemantle, Australia, June 23-25, 1999, pp. 222-227.
[124]  S.G. Ziavras and S. Krishnamurthy, "Communication Operations on the Generalized Hypercube," International Conference on Applied Informatics, Innsbruck, Austria, Febr. 15-18, 1999.
[125]  Q. Wang and S.G. Ziavras, "Network Embedding Techniques for a New Class of Feasible Parallel Architectures Capable of Very-High Performance," International Conference on Applied Informatics, Innsbruck, Austria, Febr. 15-18, 1999, pp. 566-568.
[126]  A.T. Chronopoulos, Y. Gong, H. Grebel and S.G. Ziavras, "Performance Evaluation of a 100-TeraOps Parallel System," 11th International Conference on Parallel and Distributed Computing Systems, Chicago, Illinois, Sept. 2-4, 1998, pp. 204-211.
[127]  S.G. Ziavras, "A New-Millennium Parallel Computer Capable of Very-High Performance," International Conference on Telecommunications, Porto Carras, Greece, June 21-25, 1998, pp. 255-259.
[128]  S.G. Ziavras, "Performance Analysis for an Important Class of Parallel-Processing Networks," International Symposium on Parallel Architectures, Algorithms, and Networks, Beijing, China, June 12-14, 1996, pp. 500-506.
[129]  R. Hross, S.G. Ziavras, C.N. Manikopoulos, N.J. Lad and X. Li, "A Defect Identification Algorithm for Sequential and Parallel Systems," IEEE International Symposium on Industrial Electronics, Athens, Greece, July 10-14, 1995, pp. 193-198.
[130]  S.G. Ziavras, "A Class of Scalable Architectures for High-Performance, Cost-Effective Parallel Computing," 6th IEEE Symposium on Parallel and Distributed Processing, Dallas, Texas, Oct. 26-29, 1994, pp. 162-169.
[131]  S.G. Ziavras and M.A. Sideras, "Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers," 3rd International Workshop on Parallel Image Analysis: Theory and Applications, University of Maryland, College Park, Maryland, June 7-8, 1994, pp. 263-291.
[132]  S.G. Ziavras and D.P. Shah, "Efficient Implementation of Multilevel Algorithms on Hypercube Supercomputers for Computer Vision," Workshop on Computer Architectures for Machine Perception, New Orleans, Louisiana, Dec. 15-17, 1993, pp. 313-322.
[133]  S.G. Ziavras, P. Meer and D.P. Shah, "Emulating Region-Adjacency-Graph Pyramids on Parallel Computers," Workshop on Computer Architectures for Machine Perception, New Orleans, Louisiana, Dec. 15-17, 1993.
[134]  K.C. Mouskos, J. Greenfeld and S. Ziavras, "Multi-Media Advanced Traveler Information System," Metropolitan Section of ITE, NJIT, Newark, NJ, October 1993.
[135]  K. Mouskos, J. Greenfeld and S. Ziavras, "Telephone-Based Advanced Traveler Information System," 2nd IEEE Regional Conference on Control Systems, NJIT, Newark, New Jersey, Aug. 13-14, 1993, pp. 170-193.
[136]  R. Hross, L. Prastitis and S.G. Ziavras, "Signal Analysis with a Newly Designed Electrocardiograph Using Switched Capacitor Filters," 19th IEEE Northeast Bioengineering Conference, NJIT, Newark, New Jersey, March 18-19, 1993, pp. 210-211.
[137]  N.G. Haravu and S.G. Ziavras, "Processor Allocation for a Class of Hypercube-Like Supercomputers," Supercomputing '92, Minneapolis, Minnesota, Nov. 16-20, 1992, pp. 740-749.
[138]  S.G. Ziavras, "Embedding Multilevel Structures into Massively Parallel Hypercubes-Connection Machine Results for Computer Vision Algorithms," 4th Symposium on the Frontiers of Massively Parallel Computation, McLean, Virginia, Oct. 19-21, 1992, pp. 586-589.
[139]  S.G. Ziavras, "Connection Machine Results for Pyramid Computations," Supercomputing Symposium '92, Montreal, Canada, June 7-10, 1992, pp. 296-316.
[140]  S.G. Ziavras and R.M. Anil, "Comparative Analysis of High-Speed Arithmetic Techniques for Two Classes of Networks," 23rd Annual Pittsburgh Conference on Modeling and Simulation, Pittsburgh, Pennsylvania, April 30-May 1, 1992, pp. 2353-2360.
[141]  S.G. Ziavras, S.R. Bhatt and C.N. Manikopoulos, "Algorithms for Efficient Communication in Hypercube Networks," 23rd Annual Pittsburgh Conference on Modeling and Simulation, Pittsburgh, Pennsylvania, April 30-May 1, 1992, pp. 2503-2510.
[142]  U.B. Iftikhar and S.G. Ziavras, "Efficient Arithmetic in Networks of Parallel Processors: New Algorithms and Performance Analysis," 23rd Annual Pittsburgh Conference on Modeling and Simulation, Pittsburgh, Pennsylvania, April 30-May 1, 1992, pp. 2361-2368.
[143]  S.C. Patel and S.G. Ziavras, "Comparative Analysis of Techniques that Map Hierarchical Structures into Hypercubes," ISMM International Conference on Parallel and Distributed Computing and Systems, Washington, D.C., Oct. 8-11, 1991, pp. 295-299.
[144]  P.B. Kukadia, C.N. Manikopoulos and S.G. Ziavras, "Performance Evaluation of Extended Token Ring Network Under Message Priorities," 22nd Annual Pittsburgh Conference on Modeling and Simulation, Pittsburgh, Pennsylvania, May 2-3, 1991, pp. 2280-2287.
[145]  V.S. Upadhya, C.N. Manikopoulos and S.G. Ziavras, "Improvements in Reliability and Delay with a New CIM-Based Factory Network," 22nd Annual Pittsburgh Conference on Modeling and Simulation, Pittsburgh, Pennsylvania, May 2-3, 1991, pp. 2288-2295.
[146]  N.K. Verma, C.N. Manikopoulos and S.G. Ziavras, "Comparative Study of Integrated LANs for the Hospital Environment," 22nd Annual Pittsburgh Conference on Modeling and Simulation, Pittsburgh, Pennsylvania, May 2-3, 1991, pp. 2296-2303.
[147]  S.G. Ziavras, "High Performance Mapping for Massively Parallel Hierarchical Structures," 3rd Symposium on the Frontiers of Massively Parallel Computation, College Park, Maryland, Oct. 8-10, 1990, pp. 251-254.
[148]  S.G. Ziavras, "Techniques for Mapping Deterministic Algorithms onto Multi-Level Systems," International Conference on Parallel Processing, St. Charles, Chicago, Illinois, Aug. 13-17, 1990, pp. 226-233.
[149]  S.G. Ziavras, "On the Mapping Problem for Multi-Level Systems," Supercomputing '89, Reno, Nevada, Nov. 13-17, 1989, pp. 399-408.
[150]  L.S. Davis, D. DeMenthon, T. Bestul, S. Ziavras, H.V. Srinivasan, M. Siddalingaiah and D. Harwood, "Robots Acting on Moving Bodies (RAMBO): Interaction with Tumbling Objects," NASA Conference on Space Telerobotics, Jet Propulsion Lab., Caltech, Pasadena, California, Jan. 31-Feb. 2, 1989, Vol. 1, pp. 251-260.
[151]  L.S. Davis, D. DeMenthon, T. Bestul, S. Ziavras, H.V. Srinivasan, M. Siddalingaiah and D. Harwood, "Robot Acting on Moving Bodies (RAMBO): Preliminary Results," Goddard Conference on Space Applications of Artificial Intelligence, NASA Goddard Space Flight Center, Greenbelt, Maryland, May 16-17, 1989, pp. 223-236.
[152]  S.G. Ziavras and N.A. Alexandridis, "Multigranularity Hierarchical Image Transform Architecture," 3rd International Conference on Supercomputing, Boston, Massachusetts, May 15-20, 1988, pp. 118-127.
[153]  N.A. Alexandridis and S.G. Ziavras, "Object-Quadtrees: An Efficient Structure for Processing/Transmitting Digital Images," International Conference on Digital Signal Processing, Florence, Italy, Sept. 7-10, 1987.
[154]  N.A. Alexandridis, S.G. Ziavras and P.D. Tsanakas, "Efficient Transmission of Hierarchically Structured Images Using the Walsh Hadamard Transform and Dataflow Architectures," International Conference on Communication Technology, Nanjing, China, Nov. 9-11, 1987.
[155]  N.A. Alexandridis, S.G. Ziavras and P. Tsanakas, "Architectural Adaptations for Hierarchical Image Processing/Transmission," IEEE International Conference on Communications, Toronto, Canada, June 22-25, 1986, pp. 424-428.