Synthesis of Asynchronous Controllers on FPGA from Generalized Multi-Burst Graph Specification

On promising area application of asynchronous is in Heterogeneous Systems (synchronous and asynchronous modules mixed). Asynchronous controllers are quite used in heterogeneous systems. The specification of theses controllers requires two types of signals: level sensitive signals that are used as conditionals and transition sensitive signals. Another requirement is to describe concurrency between inputs/outputs. The Multi-Burst Graph (MBG) specification allows to describing these controllers in a compact form and it is familiar to designers of digital circuits. This paper proposes a generalization in the MBG specification to increase the ability to describe the interaction between inputs/ outputs, i.e. increase the concurrency between them. This paper also proposes a method that starts from Generalized MBG specification and implements its hazard-free controllers on FPGAs. These devices have been mainly used for design of synchronous controllers. However, it is difficult to design asynchronous controllers on FPGAs, because the circuit may suffer from hazard problems. The method proposed implements this class of asynchronous controllers on FPGAs which are based on Look-Up Table (LUT) architectures. By doing this, the asynchronous circuits besides their intrinsic advantages over synchronous ones may also take advantage of integration, lower costs and short-time design associated with FPGA designs.


Introduction
There has been a gro wing interest in asynchronous circuits in recent years due to the increase in performance and complexity of dig ital systems [1]. Asynchronous circuits present several potential advantages over their synchronous counterparts: dissipate less power, do not present problems of clock skew and clock distributed network, and are mo re robust in respect to temperature variat ions and electro magnetic interactions [2]. However it is not easy to design asynchronous circuits free of hazards and critical races [2].
Two pro mising styles of asynchronous systems design are: micropipeline [3] and deco mposition (controllers+data-paths) [4]. For a set of applications, as intensive control-flow design, the decomposition style is the most appropriate. The main reason is the non-pipelined nature of the applications. For this decomposition style different techniques were proposed to the synthesis of data-paths and controllers [5]. An important class of asynchronous controllers is one that obeys the delay model, Bounded Gated and Wire Delay (BGW D) [2], [6]. This model is realistic, it allows imp lementing these circuits with basic gates.

Specifications for Asynchronous Controllers
Two important specifications for BGW D asynchronous controllers are: Signal Transition Graph (STG) and Extended Burst-Mode (XBM). STG: proposed by Chu in [7] is a Petri-net description (see Figure 1). The strength of STG is to describe concurrence between inputs and outputs (I/O concurrence) that occur in asynchronous systems. It naturally describes timing diagram that are quite used in the interfaces design. However, there are several descriptions in STG that aren't implemented. The description becomes very confusing when it has to man ipulate a larger nu mber of signals. Furthermo re, this type of description may explode in size and also the STG is not so familiar to designers of the synchronous world [8], [9]. XBM: proposed by Yun and Dill in [10] is an extension of burst-mode (BM ) specification proposed by Davis in [11] and formalized by No wick in [12] (see Figure 2). It is suitable for to describe heterogeneous (synchronous / asynchronous) systems behavior, in the case asynchronous fin ite state mach ines in Mealy type. The XBM specification solves the problems related to the STG description but the XBM allows describing a limited I/ O concurrency [1]. The XBM is the natural description of finite state machines 1 . These machines interact with the environment in generalized fundamental mode (GFM). In this mode, a new set of input signals will be activated only if the controller is in a stable state. The XBM specification added two signal types to the BM specification: directed don't-care and conditionals. The latter are level sensitive signals (LSS), i.e., they are active during their "0"or '1" phase as opposed to all others that are transition sensitive signals (TSS), i.e., they are active during the "0→1 or 1→0" transition. LSS signals may present non-monotonic behaviour. A signal is either LSS or TSS (it may NOT change from one type to the other). Very good results were presented for XBM controllers like SCSI [13], d ifferential equation solver [14] and instruction decoder [15]. Figure 2 shows the input signal Cntgt1 that is LSS and the input signals Ok, Fain, Rin are TSS.  There exist applicat ions whose behaviour contains "four phase signals" (4PS). Such signals may change fro m TSS to LSS behaviour during the controller's operation [16]. Hence, the signal is active either during its value transition (0→1, 1→0) or during its stable value (=1, =0). Vanbekbergen et al. in [17] proposed the use of 4PS signals targeting their generalized STG. One limitation of their approach is the fact that the STG description is later transformed into a SG (state graph) that grows exponentially for large problems (which is the case when non-monotonic LSS signals are present). Recently Kraus et al. in [18], [19] proposed the XBM2PLA tool for XBM machines, starting fro m a more flexib le XBM specification (F_ XBM) that accepts 4PS signals. He showed that the use of a 4PS signal reduces the size of the circuit's description producing the same result. Figure 3 shows a flexible extended burst mode specification (F_XBM) of the HP Post office benchmark, with 3 inputs (Req, Ackline, Done), 2 outputs (Sendline, Ack) and initial state 0.The input signal Done is being used in the state transition 3→0 by the transition of descent (TSS), wh ile in the state transitions 1→2 and 1→3 this signal is used by the level value (LSS). Recently, Oliveira et al. [20], [21] proposed the Multi-Burst Graph (MBG) specification. It accepts all signals types of the XBM specification and introduces burst operators. The burst operators allow the description of a limited amount of I/O concurrency. There are three types of operators: input burst OR, transition sequence (SEQ) and transition concurrence (CO). To increase the I/O concurrency it's allo wed to combine the operators CO and SEQ [21]. Oliveira et al. [22] shows that signals 4PS (F_XBM) can be incorporated into the MBG specification. Figure 4 shows a MBG specification using the CO operator (state transition: 2 → 3). It is the description in M BG o f the controller described in STG of Figure 1. The concurrency described in this example can not be captured so much in the XBM specification as also in the F_XBM specificat ion.

FPGA Implementation of B GWD Controllers
FPGAs are popular co mponents for prototyping and production of digital circuits due to their low cost and short-design time. Their focus has been on synchronous digital circu its. There have been some recent efforts to prototype asynchronous circuits on both commercial [23], [24] and academic FPGAs [25]. There are two reasons as to why off-the-shelf FPGAs are not fit to BGWD controllers [23], [26] and [27]: a. Mapping Process of hazard-free Booleans functions to logic b locks (macro-cells) may introduce logic hazards. The mapping free of logic hazard, should decomposed gates with fan-in related with LUTs [28]. Each gate is associated a LUT. Internal Routing Process among logic blocks may introduce significant delays that may result in essential hazard. Th is type of hazard can be solved by delay elements insertion or if the specification satisfied the requirement of essential signal [29].
This paper proposed a generalization of MBG specification, through of extension of SEQ operator. The extension of the SEQ gives a better interaction with the environ ment in the I/O-Mode, i.e. increases the ability of to describe the I/O concurrency. We also proposed a method that starts from generalized mult i-burst graph (GM BG) specification and synthesize asynchronous controllers. They are implemented in the feedback RS standard architecture (see Fig. 5) and interact with the environ ment in the GFM. Th is architecture is more robust to essential hazard, and the GFM enables the mapping free of logic hazard. The feedback in the RS architecture allows a covering hazard-free logic in the state transitions labelled with signals LSS and that operate with any mach ine cycle (for examp le: Input burst→ output burst // state variable) 2 . For imp lement on FPGAs the our GM BG controllers use a more robust logic min imization, where the controllers satisfy the delay model that is unbounded gate delay and bounded wire delay. This paper is structured as follo ws: section 2 presents the MBG specification, section 3 presents the GM BG specification; section 4 describes the synthesis procedure, section 5 illustrates our method with an examp le, section 6 shows our experimental results and the section 7 brings the conclusions and future works.

MBG Specification
The Multi-Burst-Graph (M BG) specificat ion belongs to a class of specifications that allow mu lt iple-input change. The MBG is an extension of the XBM. As in the XBM, MBG is represented as a state graph where each node represents a state and each arc represents a transition. Each transition in the MBG can be activated by: 1) an input burst; or 2) a burst expression. The M BG introduced three operators: input burst (OR), transition concurrence (CO) and transition sequence (SEQ). The burst expressions are based on these operators, so it increases the possibilities to describe I/O concurrency.
During the mu lti-burst transition is assumed that each output signal changes its value just once. If this assumption is not respected a functional hazard may occurs. As in the XBM, in order to guarantee the imp lementation of an M BG specification, it must obey restrictions in [20], [21]. Figure 6 shows a MBG specification, the initial state is 0. The inputs are: a, b, c and d. Where a is a level signal type and the others are transition signals type. The outputs are: x, y and z. In the state transition 5→6 is present the OR operator (T OR type). It allow or causality between the signals b and d.
In the next t ransition, 6→7, the signal b~ has an undetermined value and the signal d+ either is d=1 or d=0→1. In the state transition 2→3 the signal d* is directed don't-care. In the state transition 7→1 the signal b+ either is b=1 or b=0→1. The CO operator is present in the state transition 2→3 (T CO type). In the T CO type the bursts b+/z+ and c-d*/ y+ x+ are act ivated concurrently. The SEQ (>) operator is present in state transition 1→5 (T SEQ type). The SEQ and CO operators are presents in the state transition 4→0 (T S-C type) [22] 3 . The behaviour of CO and SEQ operators are detailed in [20], [21].

I/O Sequence Behavi or Using Burst Operators
Consider the timing diagram shown in Figure 7a This behaviour can be described by both specification, STG and XBM. This behaviour may be described in XBM defining two sequential state transitions activated by the inputs bursts (a+b*/x+y+) and (b+c+/z+) (Figure 7b). Suppose that the input burst c+ is activated immed iately after the activation of the output signal y+ as a result there is a violat ion of the I/ O-Mode. The input/output (I/O) operation mode, says in which a new input is accepted as soon as an output transition has finished. If the 3D-tool synthesizes this behaviour, so delay elements should be inserted in the line of the signal c to satisfy the I/ O-Mode. Th is procedure is not tailored for FPGAs. A mo re efficient solution consists of describing this behaviour through two sequential bursts, but activated immed iately (a+/x 1 +y 2 +) SEQ (b 1 +c 2 +/z+) exactly as the t iming diagram showed in Figure 7a. This description creates a limited degree of concurrency between an input c and the output x (Figure 7c), therefore, it operates in the I/O-Mode. This example illustrates the extension of the SEQ operator.  Figure 8 shows some descriptions of benchmark controllers in GM BG that are originally described in STG, but on the other hand, these controllers cannot be described in XBM, because the reduction of concurrency between the signals of input / output is very high, invalidating the interaction with fast environments.

Synthesis Procedure
Our controllers operate between state transitions in the GFM. In the state transitions with the SEQ operator, the controllers operate in I/O mode. Our method begins from the GM BG specification and the procedure has six steps: 1. Behavioural capture using GM BG specification; 2. Transformat ion of the GMBG into a minimu m set of MBG Flow Maps (MBG-FM MIN-SET ). It should satisfy requirements that solve all conflicts and allow hazard-free logic minimizat ion [10], [12] (see section A); 3. Codify the M BG-FM MIN-SET avoiding critical race and with the lo west number of state variables [10]; 4. Logic min imization (see section B) for each non-input signal (F SET and F RESET ); 5. Technology mapping for each non-input signal (F SET and F RESET ) [28]; 6. Structural VHDL for each non-input signal (F SET and F RESET ) [30]. Figure 9 shows the MBG-FM (2 mean don't-care) involving state transition of the T SEQ type. The cells labelled with R in the figures are reserved and they aren't part of the possible paths (inputs bursts and outputs bursts activated), although they can be used in the logic cover. The set of reserved cells allo ws each non-input signal to hold a hazard-free logic cover with basic gates.

Logic Hazard-Free Conditi ons
For each non-input signal z∈GM BG that has a transition Tj 0→1 described in M BG flow map 4 , there is a cube that completely covers the paths of all cells of value 1 (minterms). To illustrate the concept of cube, extracted fro m the state transition 0 → 1 in Figure 9, the cube of the signal x which is C TJ-X (a,b,c,x,y,z)=122220, where 2 is don't-care. The theory of hazard-free logic minimizat ion for XBM functions (f GFM-XBM ) proposed by Nowick in [12] and Yun in [10] is extended to satisfy the Theorem 1 belo w, for the two -level function f GMBG (F SET-GMBG and F RESET-GMBG ) of the feedback RS standard architecture and delay model is unbounded gate delay bounded wire delay (UGBW D).
Theorem 1: Two sufficient conditions for the implementation of hazard-free log ic circu its in the feedback RS standard architecture (see Figure 5) are: The circu it doesn't have any reached state, which is covered for more than one cube (product).
The reachable states of the circuit that form the sequence of events (0→1...1) or (1→0…0) of a non-input signal should enable only one cube (product).
Proof: Let a sum-products function f (F SET-GMBG and F RESET-GMBG ) of a non-input signal y ∈ GM BG is hazard-free functional, that presents the transitions T J ,…,T K 0→1 in the respective state transitions J,...,K and are described in the MBG flow table. M ulti-Burst Graph Specification Condition 1: Let the cubes (products) and C TJ and C TK of function f that completely cover all minterms (cells with value 1) of the respective transitions T J and T K . If C Tj ∩ C Tk =∅ then the cubes satisfy condition 1. If C TJ ∩ C TK ≠∅ then there is at least one minterm that is covered by two cubes therefore violates condition 1. If C TJ ⊂C TK then there is only the cube C TJ , therefore satisfies the condition 1.
Condition 2: If ∃ C TJ a cube that completely covers the minterms of the transition T J (J state transition) and is adjacent to the C TK cube of the K state transition, then C TJ ∪C TK that generates a cube unique that satisfies the condition 2. Assuming that in the transitions T J and T K there is the cubes C TJ and C TK not adjacent (C TJ ∩C TK =∅) and there is a path between the final states of the transitions of state J to K, so this path the not-input signal is 1→1. As in the J state transition the cube C TJ was activated and following the path until K, also the C TK cube is act ivated therefore violates condition 2, because there are two cubes activated. As in the feedback RS standard architecture allows that the next transition following the J, in case the C TJ cube being disabled, so never occurs two cubes being activated, therefore satisfies the condition 2 (cqd).
The theorem 1 shows that the f GMBG functions obtained are logic hazards-free for the specified mu lti-burst transitions types {T S , T SEQ , T CO, T S-C }. The logic cover of state transition of the type of the T OR of GM BG needs two cubes, so the delay model does not satisfy UGBWD. The theorem presented for the t ransition 0→1 is similar for the transition 1→0.

Example
In order to show our method, we used the Input D-Port Controller showed in the Figure 10a. Figure 10b show the version of this controller in GM BG specificat ion (step-1). In this examp le is applied the extension of SEQ operator .The step-2 transforms the GM BG in t wo M BG-FM they are respected the requirements. The step-3 codifies the two MBG-Flow Maps using just one state variable (Y signal) (see Figure 11). Figures 12 and 13 show respectively the Karnaugh maps for the Ri signal (R i-SET and R i-RESET ) (step 4).
R i-SET =Den.y'+Den'.y R i-RESET = Den y Rp' + Den' A i y' The decomposition wasn't necessary (trivial technology mapping -step-5). Figure 13 shows the hazard-free logic circuit of the Input D-Port Controller synthesized by our method. The functions are described in structural VHDL (step-6).

Results & Discussion
The strong of STG is to describe concurrency between inputs and outputs, important in the interaction with fast environments. The drawback is to describe decisions (input choices), by examp le, involving signals LSS, wh ich are important in heterogeneous systems, where STG can explode in the size, becoming very confusing.
The strong of XBM is to describe decisions involving signals LSS, concurrency of input signals and output signals. The drawback is to describe concurrency between signals of input and output, and sequence of signals.
The GM BG description is co mpact, not confused and it is familiar to designers of the synchronous digital circuit (based on the state diagram). The GM BG describes several types of concurrency, but still have some limitations. For example the GM BG description of the FIFO controller (Figure 8b) reduced the concurrence of the signal Ri. Figure 15a shows the original STG description of FIFO controller and Figure  15b shows the equivalent FIFO controller depicted in the Figure 8b.
Through of timing diagram of a state transition, the Figure  16 shows the capacity of the GMBG in to describe concurrency and sequence. Beister et al. in [31] presents a procedure that transforms STG in XBM. The STG o f the Figure 1 could be transformed in two XBM and just one GM BG (see Figure 4).
The Table-1 shows ten benchmarks that are described originally in STG and that were transformed in GM BG. The table contents the number of states and state transitions for the MBG transformat ion as well as the state variables, the number of LUTs and the maximu m latency time for each benchmark. These circuits were simulated in the QUARTUS II to the target EP2C35F672C7 [30]. The simu lations didn't show any hazard problem and the circu it operated as predicted in its specification. Figure 17 shows the hazard-free waveforms ext racted fro m the simu lation of the Input D-Port Controller that the logic circuit is showed in Figure 14.

Conclusions
This paper shows the MBG specification. It describes all signals types of the XBM specification and I/ O concurrence with CO and SEQ operators. The extension SEQ operator allo ws the circuit interacting with the environment in the I/O mode. We also show that mult i-burst mode controllers can be implemented on LUT-based FPGA in the BGWD class and using RS latches. For future work we intend to develop a tool for automatic synthesis. And we intend to go further on large asynchronous controllers in FPGA.